This study unveils a groundbreaking exploration of using semiconductor technology in quantum circuitry. Leveraging the unique operability of 45 nm CMOS technology at deep cryogenic temperatures (~ 300 mK), a novel quantum electronic circuit is meticulously designed. Through the intricate coupling of two matching circuits via a 45 nm nMOS transistor, operating as an open quantum system, the circuit quantum Hamiltonian and the related Heisenberg-Langevin equation are derived, setting the stage for a comprehensive quantum analysis. Central to this investigation are three pivotal coefficients derived, which are the coupling between the coupled oscillator charge and flux operators through the internal circuit of the transistor. These coefficients emerge as critical determinants, shaping both the circuit potential as a parametric amplifier and its impact on quantum properties. The study unfolds a delicate interplay between these coefficients, showcasing their profound influence on quantum discord and the gain of the parametric amplifier. Consequently, the assimilation of 45 nm CMOS technology with quantum circuitry makes it possible to potentially bridge the technological gap in quantum computing applications, where the parametric amplifier is a necessary and critical device. The designed novel quantum device serves not only as a quantum parametric amplifier to amplify quantum signals but also enhances the inherent quantum properties of the signals such as non-classicality. Therefore, one can create an effective parametric amplifier that simultaneously improves the quantum characteristics of the signals. The more interesting result is that if such a theory becomes applicable, the circuit implemented in the deep-cryogenic temperature can be easily compatible with the next step of circuitry while keeping the same electronic features compatibility with the quantum processor.
This study unveils a groundbreaking exploration of using semiconductor technology in quantum circuitry. Leveraging the unique operability of 45 nm CMOS technology at deep cryogenic temperatures (~ 300 mK), a novel quantum electronic circuit is meticulously designed. Through the intricate coupling of two matching circuits via a 45 nm nMOS transistor, operating as an open quantum system, the circuit quantum Hamiltonian and the related Heisenberg-Langevin equation are derived, setting the stage for a comprehensive quantum analysis. Central to this investigation are three pivotal coefficients derived, which are the coupling between the coupled oscillator charge and flux operators through the internal circuit of the transistor. These coefficients emerge as critical determinants, shaping both the circuit potential as a parametric amplifier and its impact on quantum properties. The study unfolds a delicate interplay between these coefficients, showcasing their profound influence on quantum discord and the gain of the parametric amplifier. Consequently, the assimilation of 45 nm CMOS technology with quantum circuitry makes it possible to potentially bridge the technological gap in quantum computing applications, where the parametric amplifier is a necessary and critical device. The designed novel quantum device serves not only as a quantum parametric amplifier to amplify quantum signals but also enhances the inherent quantum properties of the signals such as non-classicality. Therefore, one can create an effective parametric amplifier that simultaneously improves the quantum characteristics of the signals. The more interesting result is that if such a theory becomes applicable, the circuit implemented in the deep-cryogenic temperature can be easily compatible with the next step of circuitry while keeping the same electronic features compatibility with the quantum processor.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
In this study, we present the design and analysis of a Low Noise Amplifier tailored specifically for quantum applications. We selected the HEMT for its unique noise reduction properties, crucial for quantum engineering. The main goal is to minimize the noise figure within the C-band frequency range (4-8 GHz) to induce nonclassicality in quantum signals. While achieving a noise figure of less than 0.065 dB within this band, we recognized the trade-off with gain, mitigated by incorporating additional stages to maintain noise figure at optimal levels. Quantum analysis of the circuit, employing a simplified model of HEMT due to its complexity, revealed insights into its nonlinear properties and interactions between circuit components and environmental factors. Leveraging Qutip toolbox in Python, we conducted time-evolution analysis of the system, revealing the circuit's behavior as an open quantum system under cryogenic conditions. Our investigation extends to quantifying quantum correlation (quantum discord) and its relationship with noise figure, posing important questions regarding the direct impact of its minimization on circuit nonclassicality at cryogenic temperatures. This comprehensive study sheds light on the intricate interplay between circuit design, and its influence on the relationship between the noise figure and quantum correlation.
This study presents a comprehensive design approach focusing on quantum chip signal amplification by Josephson parametric amplifiers, and an integrated receiver for detecting ultra-low-level quantum signals. Quantum theory is used to analyze the dynamics of a transmon qubit coupled to a transmission line, entanglement between them, and design a parametric amplifier to amplify the quantum signals. Integration of these quantum devices with a 45 nm CMOS system-on-chip receiver creates a sophisticated blend of quantum and classical elements. The transmon qubit and parametric amplifier as a quantum chip, operating at 10 mK, are evaluated for key quantum metrics such as entanglement, Stoke projector probabilities, and parametric amplifier gain. Simultaneously, the resulting receiver combines high-performance components, including a low-noise amplifier with 0.76 dB noise figure in a broad bandwidth, a sweepable 5.0 GHz sinusoidal wave generator, and a purpose-designed mixer for C-band to zero-intermediate frequency (IF) conversion. An intermediate frequency amplifier with flat 26 dB gain and its low-pass filter property generates a pure sinusoidal wave at zero-IF, suitable for subsequent processing at room temperature. This design achieves a notable balance with low power consumption (∼122 mW), a noise figure less than 0.9 dB, high gain (∼65 dB), a wide bandwidth of 3.6 GHz, and compact dimensions (0.6 × 0.4 mm2). The fully integrated receiver, capable of reading out at least 90 qubits, positions this design for potential applications in quantum computing. Post-simulation validations at room temperature underscore the promising and innovative nature of this approach.
Thousands to millions of sensitive signals will need to be conveyed through all the temperature stages of a dilution fridge to operate future large-scale quantum processors made of many quantum bits. The exploding number of heat-conductive coaxial cables will overwhelm the fridge cooling capabilities, detrimental to the quantum core. Moving the control electronics down to cryogenic temperatures allows the use of already-available superconducting cables, alleviating heat conduction between low-temperature stages, and appears as a clear path towards scalability in the number of operating qubits.This Ph.D. work aimed to explore the use of the industrial CMOS 28nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology at cryogenic temperatures for quantum computing applications. Our first objective is to extend the sparse existing knowledge about the FD-SOI 28nm transistors at cryogenic temperatures for practical aspects of circuit design and later for developments of compact models.To speed-up the characterization of single devices with the inherent hour-long cooling cycles, we designed an integrated circuit multiplexing a thousand of transistors for different geometries and gate-stack flavors for low-frequency measurement of the current-voltage characteristics and pair-matching analysis from 300 down to 0.1K. We discuss and analyze the evolution trends with varying geometry at different temperatures for important quantities in circuit design, such as the transconductance, the conductance, and the transconductance over drain current ratio of individual transistors.Secondly, we explore the low-temperature co-integration and the full on-chip integration of semiconductor quantum devices with classical electronics aimed at specific measurements down to the millikelvin range.We first focus on the sub-nanoampere current measurement of quantum dot devices by designing and characterizing a low-power transimpedance amplifier (TIA). The high-gain amplifier is successfully applied to measure the current across single- and double quantum-dot devices, respectively wire-bonded a few mm away or on-chip integrated a few micrometers-away. To further leverage the integration into the same substrate, we connected GHz-range voltage-controlled oscillators to one of the gates of the double dot in an attempt to observe discrete charge pumping in a fully-integrated device.Lastly, we tackled the measurement of the gate capacitance of single quantum devices by proposing a new measurement scheme making use of the cryogenic electronics capabilities as an alternative to the well-known reflectometry. By integrating a voltage-controlled current excitation and a voltage-sensing amplifier in the 200 MHz range, both in close proximity to the quantum device connected to an LC tank, the read-out circuitry of a variation in the device capacitance becomes a purely lumped-element system with impedance measurement of the resonant circuit without any wave propagation like in reflectometry. This approach increases simplicity and compactness of the measurement set-up. We even replace the bulky passive inductor used in reflectometry by an active inductor made of transistors and capacitors, offering improved scalability with a 3-orders of magnitude lower area for the same inductance. The resulting circuit successfully measured aF-capacitance variations of nanometric transistors at 4.2K revealing oscillatory quantum effects in the gate capacitance as a function of the gate and back-gate voltages.At the end of this dissertation, a picture is given with the challenges laying ahead related to circuit architecture and design for the ultimate goal of entering into the era of large-scale quantum processing.
Most quantum computing platforms are nowadays operating at temperatures of a few Kelvin or lower, and their control and readout electronics are gradually brought close or to the same temperature stages. A pivotal step towards the design of such CMOS circuits is the NMOS and PMOS transistor characterization at cryogenic temperatures. While typically performed in cryogenic probe stations down to liquid helium temperature, the CMOS chip for quantum computing is cooled further along with the qubit sample in dilution refrigerators. Here we propose and discuss a wire-bonded and packaged CMOS characterization setup down to 10mK. Several NMOS and PMOS transistors with various aspect ratios of a 180nm CMOS series die were characterized, to develop a novel PDK model for circuit design.
Quantum computing is a fascinating and rapidly evolving field of technology that promises to revolutionize many areas of science, engineering, and society. The fundamental unit of quantum computing is the quantum bit that can exist in two or more states concurrently, as opposed to a classical bit that can only be either 0 or 1. Any subatomic element, including atoms, electrons, and photons, can be used to implement qubits. The chosen sub-atomic elements should have quantum mechanical properties. Most commonly, photons have been used to implement qubits. Qubits can be manipulated and read by applying external fields or pulses, such as lasers, magnets, or microwaves. Quantum computers are currently suffering from various complications such as size, operating temperature, coherence problems, entanglement, etc. The realization of quantum computing, a novel paradigm that uses quantum mechanical phenomena to do computations that are not possible with classical computers, is made possible, most crucially, by the need for a quantum processor and a quantum SOC. As a result, Cryo-CMOS technology can make it possible to integrate a Quantum system on a chip. Cryo-CMOS devices are electronic circuits that operate at cryogenic temperatures, usually below 77 K (−196 °C).