Quantum computing has shown promise in solving complex problems by leveraging the principles of superposition and entanglement. Variational quantum algorithms (VQA) are a class of algorithms suited for near-term quantum computers due to their modest requirements of qubits and depths of computation. This paper introduces Tetris – a compilation framework for VQA applications on near-term quantum devices. Tetris focuses on reducing two-qubit gates in the compilation process since a two-qubit gate has an order of magnitude more significant error and execution time than a single-qubit gate. Tetris exploits unique opportunities in the circuit synthesis stage often overlooked by the state-of-the-art VQA compilers for reducing the number of two-qubit gates. Tetris comes with a refined IR of Pauli string to express such a two-qubit gate optimization opportunity. Moreover, Tetris is equipped with a fast bridging approach that mitigates the hardware mapping cost. Overall, Tetris demonstrates a reduction of up to $41.3 \%$ in CNOT gate counts, $37.9 \%$ in circuit depth, and $\mathbf{4 2. 6 \%}$ in circuit duration for various molecules of different sizes and structures compared with the state-of-the-art approaches. Tetris is open-sourced at this link.
Quantum computing has shown promise in solving complex problems by leveraging the principles of superposition and entanglement. Variational quantum algorithms (VQA) are a class of algorithms suited for near-term quantum computers due to their modest requirements of qubits and depths of computation. This paper introduces Tetris – a compilation framework for VQA applications on near-term quantum devices. Tetris focuses on reducing two-qubit gates in the compilation process since a two-qubit gate has an order of magnitude more significant error and execution time than a single-qubit gate. Tetris exploits unique opportunities in the circuit synthesis stage often overlooked by the state-of-the-art VQA compilers for reducing the number of two-qubit gates. Tetris comes with a refined IR of Pauli string to express such a two-qubit gate optimization opportunity. Moreover, Tetris is equipped with a fast bridging approach that mitigates the hardware mapping cost. Overall, Tetris demonstrates a reduction of up to 41.3% in CNOT gate counts, 37.9% in circuit depth, and 42.6% in circuit duration for various molecules of different sizes and structures compared with the state-of-the-art approaches. Tetris is open-sourced at this link.
Variational quantum algorithms (VQAs) hold significant promise for solving complex problems across diverse fields. However, their practical implementation on near-term quantum devices is severely hampered by the pervasive effects of quantum noise. Traditional quantum circuit compilation techniques are largely static, failing to account for the unique noise profiles inherent in individual quantum hardware. This paper introduces a novel adaptive quantum circuit compilation framework designed to mitigate these limitations. The core concept centers around dynamically adjusting the circuit layout and gate decomposition in real-time, leveraging measurements of the quantum hardware's noise characteristics to optimize both the accuracy and circuit depth of the compiled quantum circuit. This approach represents a critical step towards unlocking the full potential of VQAs by enabling them to effectively operate within the constraints of noisy quantum computers. The framework incorporates feedback loops for continuous refinement, adapting to evolving noise conditions. The methodology is described, focusing on the key components: noise profiling, adaptive gate decomposition, and circuit re-optimization. Simulation results demonstrate the effectiveness of the adaptive approach in reducing circuit depth and improving the fidelity of VQA computations compared to static compilation methods. This work lays the foundation for robust and efficient VQA execution on future quantum hardware.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
Variational quantum algorithms (VQA) based on Hamiltonian simulation represent a specialized class of quantum programs well-suited for near-term quantum computing applications due to its modest resource requirements in terms of qubits and circuit depth. Unlike the conventional single-qubit (1 Q) and two-qubit (2 Q) gate sequence representation, Hamiltonian simulation programs are essentially composed of disciplined subroutines known as Pauli exponentiations (Pauli strings with coefficients) that are variably arranged. To capitalize on these distinct program features, this study introduces PHOENIX, a highly effective compilation framework that primarily operates at the high-level Pauli-based intermediate representation (IR) for generic Hamiltonian simulation programs. PHOENIX exploits global program optimization opportunities to the greatest extent, compared to existing SOTA methods despite some of them also utilizing similar IRs. PHOENIX employs the binary symplectic form (BSF) to formally describe Pauli strings and reformulates IR synthesis as reducing the column weights of BSF by appropriate Clifford transformations. It comes with a heuristic BSF simplification algorithm that searches for the most appropriate 2Q Clifford operators in sequence to maximally simplify the BSF at each step, until the BSF can be directly synthesized by basic 1 Q and 2Q gates. PHOENIX further performs a global ordering strategy in a TETRIS-like fashion for these simplified IR groups, carefully balancing optimization opportunities for gate cancellation, minimizing circuit depth, and managing qubit routing overhead. Experimental results demonstrate that PHOENIX outperforms SOTA VQA compilers across diverse program categories, backend ISAs, and hardware topologies.
Quantum circuit mapping on Noisy Intermediate-Scale Quantum (NISQ) devices must satisfy physical connectivity constraints while minimizing both SWAP overhead and exposure to transient faults like decoherence. Existing compilers typically optimize qubit routing and noise-aware placement independently, failing to jointly exploit spatial structure to reduce both SWAP depth and idle-time-induced decoherence. We introduce TETRIS-Q, a mapping framework that partitions the physical qubit topology into local rectangular tiles. This tiling abstraction enables a unified strategy: tile-local mapping minimizes idle qubit lifetimes, while cross-tile parallel scheduling maximizes concurrent two-qubit gate execution. By treating transient-fault probability as a function of idle duration and gate ordering, rather than just circuit depth, TETRIS-Q jointly penalizes SWAP count and cumulative idle time. On grid-heavy architectures, we project a 10–30% reduction in SWAP count [to verify] and measurable fidelity improvements over routing-only baselines [to verify]. This approach demonstrates that spatial tiling offers a robust paradigm for high-fidelity NISQ compilation. ## 1. Introduction Compiling quantum algorithms for Noisy Intermediate-Scale Quantum (NISQ) hardware requires mapping logical qubits onto physical qubits with limited connectivity. To execute gates between non-adjacent physical qubits, compilers insert SWAP gates—operations that exchange qubit states—to route interacting qubits into adjacency. While SWAP gates introduce additional circuit depth and gate errors, they also indirectly increase exposure to transient faults (decoherence and relaxation, characterized by T1 and T2 timescales) by extending the duration that idle qubits wait for dependent operations. Existing quantum compilers generally treat routing minimization and noise-aware placement as separate optimization passes. However, this independent optimization misses opportunities to exploit the spatial locali
Quantum Approximation Optimization Algorithm (QAOA) is a highly advocated variational algorithm for solving the combinatorial optimization problem. One critical feature in the quantum circuit of QAOA algorithm is that it consists of two-qubit operators that commute. The flexibility in reordering the two-qubit gates allows compiler optimizations to generate circuits with better depths, gate count, and fidelity. However, it also imposes significant challenges due to additional freedom exposed in the compilation. Prior studies lack the following: (1) Performance guarantee, (2) Scalability, and (3) Awareness of regularity in scalable hardware. We propose a structured method that ensures linear depth for any compiled QAOA circuit on multi-dimensional quantum architectures. We also demonstrate how our method runs on Google Sycamore and IBM Non-linear architectures in a scalable manner and in linear time. Overall, we can compile a circuit with up to 1024 qubits in 10 seconds with a 3.8X speedup in depth, 17% reduction in gate count, and 18X improvement for circuit ESP.
Currently developed quantum devices have the potential to show a computational advantage if quantum applications exploit the devices efficiently. Variational quantum algorithms (VQAs) combine a quantum processor with a classical computer to minimize the expectation value of a problem Hamiltonian. An important element of VQAs is the state-preparation circuit, referred to as variational quantum circuit. To improve the ability for solving combinatorial optimizations with VQAs, we show that the variational quantum circuit with single-qubit gates only can find the ground state more quickly. We demonstrate our VQA by using real quantum processors through IBM Quantum. As a result, the variational circuit with single-qubit gates takes four times smaller numbers of function evaluations than that with entangling gates, such as controlled-X gates.