Abstract As quantum computing hardware steadily increases in qubit count and quality, one important question is how to allocate these resources to mitigate the effects of hardware noise. In a transitional era between noisy small-scale and fully fault-tolerant systems, we envisage a scenario in which we are only able to error-correct a fraction of the qubits required to perform an interesting computation. In this work, we develop concrete constructions of logical operations on a joint system of a collection of noisy and a collection of error-corrected logical qubits. Within this setting and under Pauli noise assumptions, we provide analytic evidence that brick-layered circuits display on average slower concentration to the “useless” uniform distribution with increasing circuit depth compared to fully noisy circuits. We corroborate these findings by numerical demonstration of slower decoherence with an increasing fraction of error-corrected qubits under depolarizing noise acting at the circuit level. We find that this advantage only manifests when the number of error-corrected qubits passes a specified threshold which depends on the number of couplings between error-corrected and noisy registers.
Abstract As quantum computing hardware steadily increases in qubit count and quality, one important question is how to allocate these resources to mitigate the effects of hardware noise. In a transitional era between noisy small-scale and fully fault-tolerant systems, we envisage a scenario in which we are only able to error-correct a fraction of the qubits required to perform an interesting computation. In this work, we develop concrete constructions of logical operations on a joint system of a collection of noisy and a collection of error-corrected logical qubits. Within this setting and under Pauli noise assumptions, we provide analytic evidence that brick-layered circuits display on average slower concentration to the “useless” uniform distribution with increasing circuit depth compared to fully noisy circuits. We corroborate these findings by numerical demonstration of slower decoherence with an increasing fraction of error-corrected qubits under depolarizing noise acting at the circuit level. We find that this advantage only manifests when the number of error-corrected qubits passes a specified threshold which depends on the number of couplings between error-corrected and noisy registers.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.
Quantum error correction is necessary to perform large-scale quantum computations in the presence of noise and decoherence. As a result, several aspects of quantum error correction have already been explored. These have been primarily studies of quantum memory[1, 2], an important first step towards quantum computation, where the objective is to increase the lifetime of the encoded quantum information. Additionally, several works have explored the implementation of logical gates[3-5]. In this work we study a next step - fault-tolerantly implementing quantum circuits. We choose the [[4,1,2]] Bacon-Shor subsystem code, which has a particularly simple error-detection circuit. Through both numerics and site-counting arguments, we compute pseudo-thresholds for the Pauli error rate p in a depolarizing noise model, below which the encoded circuits outperform the unencoded circuits. These pseudo-threshold values are shown to be as high as p=3% for short circuits, and p=0.6% for circuits of moderate depth. Additionally, we see that multiple rounds of stabilizer measurements give an improvement over performing a single round at the end. This provides a concrete suggestion for a small-scale fault-tolerant demonstration of a quantum algorithm that could be accessible with existing hardware.
The promise of quantum computers hinges on the ability to scale to large system sizes, e.g., to run quantum computations consisting of more than 100 million operations fault-tolerantly. This in turn requires suppressing errors to levels inversely proportional to the size of the computation. As a step towards this ambitious goal, we present experiments on a trapped-ion QCCD processor where, through the use of fault-tolerant encoding and error correction, we are able to suppress logical error rates to levels below the physical error rates. In particular, we entangled logical qubits encoded in the [[7,1,3]] code with error rates 9.8 times to 500 times lower than at the physical level, and entangled logical qubits encoded in a [[12,2,4]] code based on Knill's C4/C6 scheme with error rates 4.7 times to 800 times lower than at the physical level, depending on the judicious use of post-selection. Moreover, we demonstrate repeated error correction with the [[12,2,4]] code, with logical error rates below physical circuit baselines corresponding to repeated CNOTs, and show evidence that the error rate per error correction cycle, which consists of over 100 physical CNOTs, approaches the error rate of two physical CNOTs. These results signify a transition from noisy intermediate scale quantum computing to reliable quantum computing, and demonstrate advanced capabilities toward large-scale fault-tolerant quantum computing.
When error correction becomes possible it will be necessary to dedicate a large number of physical qubits to each logical qubit. Error correction allows for deeper circuits to be run, but each additional physical qubit can potentially contribute an exponential increase in computational space, so there is a trade-off between using qubits for error correction or using them as noisy qubits. In this work we look at the effects of using noisy qubits in conjunction with noiseless qubits (an idealized model for error-corrected qubits), which we call the "clean and dirty" setup. We employ analytical models and numerical simulations to characterize this setup. Numerically we show the appearance of Noise-Induced Barren Plateaus (NIBPs), i.e., an exponential concentration of observables caused by noise, in an Ising model Hamiltonian variational ansatz circuit. We observe this even if only a single qubit is noisy and given a deep enough circuit, suggesting that NIBPs cannot be fully overcome simply by error-correcting a subset of the qubits. On the positive side, we find that for every noiseless qubit in the circuit, there is an exponential suppression in concentration of gradient observables, showing the benefit of partial error correction. Finally, our analytical models corroborate these findings by showing that observables concentrate with a scaling in the exponent related to the ratio of dirty-to-total qubits.
Effective error correction is required to mitigate the effects of physical noise and safeguard logical qubits for fault-tolerant computation in order to realize large-scale quantum computers. Because physical gate defects, measurement mistakes, leakage errors, and correlated noise can propagate across processing levels, single-level quantum error correction is typically not appropriate for large-scale quantum structures. This research proposes a multi-level quantum error correction framework for scalable quantum computing architectures. Physical-layer syndrome extraction, logical-layer stabilizer decoding, and architecture-level error propagation control are the methods used. To minimize the buildup of logical errors in the deep circuit and under qubit connection limits, a multi-level decoding technique is employed. According to the simulation results, the suggested framework increases the fault-tolerant circuit success rate by 12.6% over single-level correction and has a logical error rate of 1.7×10⁻5 under a physical error rate of 10⁻³. According to the research, a large-scale quantum computing system can be made more reliable by utilizing many tiers of quantum error correction.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.