The synthesis approaches for quantum circuits typically aim at minimizing the number of lines or gates. Given the tight restrictions on those logical resources in physical implementations, we propose to view the problem fundamentally different: Given noisy gates and a fixed number of lines, how can we use them to perform a computation as precisely as possible? In this paper we show approximate circuits can be deployed for computations with limited resources. Performing experiments on a QC simulator, we show that under the influence of noise, approximate circuits can have lower error-rates than exact circuits.
The synthesis approaches for quantum circuits typically aim at minimizing the number of lines or gates. Given the tight restrictions on those logical resources in physical implementations, we propose to view the problem fundamentally different: Given noisy gates and a fixed number of lines, how can we use them to perform a computation as precisely as possible? In this paper we show approximate circuits can be deployed for computations with limited resources. Performing experiments on a QC simulator, we show that under the influence of noise, approximate circuits can have lower error-rates than exact circuits.
The quantum circuit synthesis problem bridges quantum algorithm design and quantum hardware implementation in the Noisy Intermediate-Scale Quantum (NISQ) era. In quantum circuit synthesis problems, diagonal unitary synthesis plays a crucial role due to its fundamental and versatile nature. Meanwhile, experimental results have shown that moderately approximating the original algorithm to conserve quantum resources can improve the fidelity of algorithms during quantum execution. Building on this insight, we propose a quantum circuit synthesis algorithm to design diagonal unitary implementations based on specified quantum resource limits. Our algorithm can synthesize diagonal unitary for quantum circuits with up to 15 qubits on an ordinary laptop. In algorithm efficiency, synthesizing an n-qubit unitary matrix with an exact algorithm requires 2n CNOT gates as a baseline. Within the algorithm error $\varepsilon $ range of interest (0\%-12\%), our algorithm achieves a $3.2\varepsilon $ reduction in CNOT gates on average. In runtime, the algorithm efficiently performs, synthesizing 12-qubit diagonal unitary in an average of 6.57 seconds and 15-qubit in approximately 561.71 seconds.
Noisy intermediate-scale quantum (NISQ) computers face significant reliability challenges because they are vulnerable to quantum noise, which severely limits their fidelity in quantum applications. In particular, deep circuits with a large number of quantum gates are susceptible to errors as they are more likely to lose their states in a deep circuit. In this paper, we propose a quantum circuit for square root operation that generates correct results on NISQ devices. The square root operation is used in many applications such as complex number computations, computer graphics, etc. While there have been limited studies on quantum square root circuits, none of them can be implemented on NISQ devices. In this work, we simplify the structure of an exact quantum square root circuit and reduce the number of quantum gates. The proposed design reduces the complexity of the square root circuit while maintaining the same level of precision in outputs. In addition, we exploit approximate computing to simplify the circuit further and run it on a real quantum computer. Approximate computing is used in classical computers to enhance the power and/or performance in exchange for accuracy. We exploit approximate computing for a different purpose, which is reducing the depth as well as the number of quantum gates in the square root circuit. To validate the effectiveness of our approach, we conduct experiments on an IBM quantum computer, where our circuit produces meaningful results. Furthermore, we present examples of error-resilient applications to demonstrate the validity of our approximate circuit.
In the near future of the noisy intermediate-scale quantum (NISQ) era, almost all quantum computing devices will be restricted to a specific fixed qubits connectivity architecture. Thus, the synthesis of quantum circuits with limited connectivity is urgent. We design quantum circuit synthesis algorithms for basic and essential synthesis problems, such as quantum state preparation, general unitary synthesis, and quantum isometries. For any architecture, the controlled not (cnot) count is at most 5/3 times the state-of-the-art result on complete-graph architecture. For some specific architectures, such as square-grid ones, the ratio is reduced to 1.126. The numerical simulation result is confirmatory of theoretical conclusions. Our algorithms significantly reduce by more than 50 additional cnot count compared to mapping algorithms. These algorithms help to implement the larger-scale algorithm in the physics device. Our results illustrate that well-designed synthesis algorithms can mitigate the problem of limited qubit connectivity in the NISQ era and may suggest the design of large-scale quantum devices.
Synthesis of reversible circuits is an active research area motivated by its applications e.g. in quantum computation or low-power design. The number of used circuit lines is thereby a crucial criterion. In this paper, we introduce several methods (including a theoretical upper bound) for the efficient computation or at least approximation of the minimal number of lines needed to realize a given function in reversible logic. While the proposed exact approach requires a significant amount of run-time (exponential in the worst case), the heuristic methods lead to very precise approximations in very short run-time. Using this, it can be shown that current synthesis approaches for large functions are still far away from producing optimal circuits with respect to the number of lines.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Abstract This work presents a resource-efficient architecture for quantum 5:2 compressors, addressing the prohibitively high T-count and circuit depth of exact arithmetic in the Noisy Intermediate-Scale Quantum (NISQ) regime. We implement a Hybrid Approximate-Exact synthesis methodology that fundamentally alters the logic synthesis path to prioritize quantum cost over strict logical equivalence. The proposed design intentionally isolates and excludes the fourth input bit (í µí±¥ 4)from the critical carry computation path during the initial approximation stage, significantly pruning the required Toffoli gate count. To mitigate the induced error, the proposed approach integrate a dedicated Error Correction Module (ECM) based on half-adder logic that realigns the significance weights of the intermediate sum and carry vectors. Validation via Qiskit Aer exhaustive statevector simulation confirms that this architecture achieves a superior Pareto frontier between circuit fidelity and arithmetic precision compared to fully exact baselines. The resulting topology minimizes decoherence-induced errors by reducing the gate depth, providing a viable arithmetic primitive for error-tolerant quantum algorithms.