Bosonic cat qubits stabilized by two-photon driven dissipation benefit from exponential suppression of bit-flip errors and an extensive set of gates preserving this protection. These properties make them promising building blocks of a hardware-efficient and fault-tolerant quantum processor. In this paper, we propose a performance optimization of the repetition cat code architecture using fast but noisy CNOT gates for stabilizer measurements. This optimization leads to high thresholds for the physical figure of merit, given as the ratio between intrinsic single-photon loss rate of the bosonic mode and the engineered two-photon loss rate, as well as an improved scaling below threshold of the required overhead, to reach an expected level of logical error rate. Relying on the specific error models for cat qubit operations, this optimization exploits fast parity measurements, using accelerated low-fidelity CNOT gates, combined with fast ancilla parity-check qubits. The significant enhancement in the performance is explained by: 1- the highly asymmetric error model of cat qubit CNOT gates with a major component on control (ancilla) qubits, and 2- the robustness of the repetition cat code error correction performance in presence of the leakage induced by fast operations. In order to demonstrate these performances, we develop a method to sample the repetition code under circuit-level noise that also takes into account cat qubit state leakage.
Bosonic cat qubits stabilized by two-photon driven dissipation benefit from exponential suppression of bit-flip errors and an extensive set of gates preserving this protection. These properties make them promising building blocks of a hardware-efficient and fault-tolerant quantum processor. In this paper, we propose a performance optimization of the repetition cat code architecture using fast but noisy CNOT gates for stabilizer measurements. This optimization leads to high thresholds for the physical figure of merit, given as the ratio between intrinsic single-photon loss rate of the bosonic mode and the engineered two-photon loss rate, as well as an improved scaling below threshold of the required overhead, to reach an expected level of logical error rate. Relying on the specific error models for cat qubit operations, this optimization exploits fast parity measurements, using accelerated low-fidelity CNOT gates, combined with fast ancilla parity-check qubits. The significant enhancement in the performance is explained by: 1- the highly asymmetric error model of cat qubit CNOT gates with a major component on control (ancilla) qubits, and 2- the robustness of the repetition cat code error correction performance in presence of the leakage induced by fast operations. In order to demonstrate these performances, we develop a method to sample the repetition code under circuit-level noise that also takes into account cat qubit state leakage.
Quantum processors rely on controllable quantum systems, which are prone to many kinds of errors, partly due to the environment, and therefore require quantum error correction with many physical resources to operate fault-tolerantly.To reduce physical errors hence resource overheads, bosonic encodings have emerged, taking advantage of the infinitely large Hilbert space of harmonic oscillators for intrinsic autonomous error correction.However, with such infinite systems, capturing the physics of gates and error processes becomes challenging, and classical simulations require taking into account many excited states of the Hilbert space to model their dynamics.Besides, for the quantum error correction to work, the level of noise has to be below a constant value called the accuracy threshold.Optimizing the implementation of a quantum computer based on the concatenation of such a bosonic code with a multi-qubit code is two-fold.First, one can optimize the physical systems and their dynamics which require tools to simulate their behavior accurately.Second, one can optimize the quantum error correction code to increase the threshold value hence easing the experimental requirements for the construction of a large-scale quantum computer.In this thesis, we propose and analyze analytical and numerical methods for the simulation of the repetition cat code, both at the physical level of the cat qubit and also at the logical level of the multi-qubit code, and design a performance optimization for the code.The protection against the environment induced noise is achieved via a two-photon dissipation confinement, which protects arbitrarily well the cat qubit against bit-flip errors with the average number of photons in the cat state.To simulate the dynamics of composite cat-qubit systems, we rely on the invariant operators of this dissipation and design a numerical method based on a perturbation analysis with an asymptotic expansion exploiting the formulation of the slow dynamics of reduced dimension.The repetition code implemented using cat qubits then protects against phase-flips.We propose a performance optimization of the repetition cat code architecture using fast ancilla and fast but noisy CNOT gates for parity measurements, leading to high thresholds as well as a better sub-threshold logical error suppression and demonstrate its robustness in presence of the leakage by developing a new sampling method.
We estimate and analyze the error rates and the resource overheads of the repetition cat qubit approach to universal and fault-tolerant quantum computation. The cat qubits stabilized by two-photon dissipation exhibit an extremely biased noise where the bit-flip error rate is exponentially suppressed with the mean number of photons. In a recent work we suggested that the remaining phase-flip error channel could be suppressed using a one-dimensional repetition code. Indeed, using only bias-preserving gates on the cat qubits, it is possible to build a universal set of fault-tolerant logical gates at the level of the repetition cat qubit. In this paper we perform Monte Carlo simulations of all the circuits implementing the protected logical gates, using a circuit-level error model. Furthermore, we analyze two different approaches to implement a fault-tolerant Toffoli gate on repetition cat qubits. These numerical simulations indicate that very low logical error rates could be achieved with a reasonable resource overhead, and with parameters that are within the reach of near-term circuit QED experiments.
To solve problems of practical importance1,2, quantum computers probably need to incorporate quantum error correction, in which a logical qubit is redundantly encoded in many noisy physical qubits3–5. The large physical-qubit overhead associated with error correction motivates the search for more hardware-efficient approaches6–18. Here, using a superconducting quantum circuit19, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d = 5 (ref. 10). A stabilizing circuit passively protects cat qubits against bit flips20–24. The repetition code, using ancilla transmons for syndrome measurement, corrects cat qubit phase flips. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below the threshold. The logical bit-flip error is suppressed with increasing cat qubit mean photon number, enabled by our realization of a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the distance-5 code. Despite the increased number of fault locations of the distance-5 code, the high degree of noise bias preserved during error correction enables comparable performance. These results, where the intrinsic error suppression of the bosonic encodings enables us to use a hardware-efficient outer error-correcting code, indicate that concatenated bosonic codes can be a compelling model for reaching fault-tolerant quantum computation. Bosonic qubits can be engineered to feature intrinsic protection against certain kinds of errors, which makes quantum error correction across many bosonic qubits possible with less overhead.
Cat qubits can exhibit strong noise bias due to their exponentially enhanced bit-flip times and only polynomially reduced phase-flip times with increasing photon number, which makes them attractive candidates for hardware-efficient quantum error correction. However, it is difficult to maintain this strong noise bias in logical operations such as CNOT gates between cats. Here, we propose a coherent CNOT gate scheme between two dissipative cats that preserves the exponential noise bias. The proposed gate relies only on unitary operations, which avoids the non-idealities associated with many existing gate schemes that rely on engineered dissipations. Assuming good component lifetimes and precise nonlinearity engineering, the proposed gate can enable logical memory in the megaquop regime (logical error rates < 10^-6) with a distance-7 repetition code consisting of 13 cat qubits.
Stabilized cat qubits that possess biased noise channel with bit-flip errors exponentially smaller than phase-flip errors. Together with a set of bias-preserving (BP) gates, cat qubits are a promising candidate for realizing hardware efficient quantum error correction and fault-tolerant quantum computing. Compared to dissipatively stabilized cat qubits, the Kerr cat qubits can in principle support faster gate operations with higher gate fidelity, benefiting from the large energy gap that protects the code space. However, the leakage of the Kerr cats can increase the minor type of errors and compromise the noise bias. Both the fast implementation of gates and the interaction with environment can lead to such detrimental leakage if no sophisticated controls are applied. In this work, we introduce new fine-control techniques to overcome the above obstacles for Kerr cat qubits. To suppress the gate leakage, we use the derivative-based transition suppression technique to design derivative-based controls for the Kerr BP gates. We show that the fine-controlled gates can simultaneously have high gate fidelity and high noise bias and when applied to concatenated quantum error correction, can not only improve the logical error rate but also reduce resource overhead. To suppress the environment-induced leakage, we introduce colored single-photon dissipation, which can continuously cool the Kerr cats and suppress the minor errors while not enhancing the major errors.
We present a 1D repetition code based on the so-called cat qubits as a viable approach toward hardwareefficient universal and fault-tolerant quantum computation.The cat qubits that are stabilized by a twophoton driven-dissipative process exhibit a tunable noise bias where the effective bit-flip errors are exponentially suppressed with the average number of photons.We propose a realization of a set of gates on the cat qubits that preserve such a noise bias.Combining these base qubit operations, we build, at the level of the repetition cat qubit, a universal set of fully protected logical gates.This set includes single-qubit preparations and measurements, NOT, controlled-NOT, and controlled-controlled-NOT (Toffoli) gates.Remarkably, this construction avoids the costly magic state preparation, distillation, and injection.Finally, all required operations on the cat qubits could be performed with slight modifications of existing experimental setups.