We estimate and analyze the error rates and the resource overheads of the repetition cat qubit approach to universal and fault-tolerant quantum computation. The cat qubits stabilized by two-photon dissipation exhibit an extremely biased noise where the bit-flip error rate is exponentially suppressed with the mean number of photons. In a recent work we suggested that the remaining phase-flip error channel could be suppressed using a one-dimensional repetition code. Indeed, using only bias-preserving gates on the cat qubits, it is possible to build a universal set of fault-tolerant logical gates at the level of the repetition cat qubit. In this paper we perform Monte Carlo simulations of all the circuits implementing the protected logical gates, using a circuit-level error model. Furthermore, we analyze two different approaches to implement a fault-tolerant Toffoli gate on repetition cat qubits. These numerical simulations indicate that very low logical error rates could be achieved with a reasonable resource overhead, and with parameters that are within the reach of near-term circuit QED experiments.
We estimate and analyze the error rates and the resource overheads of the repetition cat qubit approach to universal and fault-tolerant quantum computation. The cat qubits stabilized by two-photon dissipation exhibit an extremely biased noise where the bit-flip error rate is exponentially suppressed with the mean number of photons. In a recent work we suggested that the remaining phase-flip error channel could be suppressed using a one-dimensional repetition code. Indeed, using only bias-preserving gates on the cat qubits, it is possible to build a universal set of fault-tolerant logical gates at the level of the repetition cat qubit. In this paper we perform Monte Carlo simulations of all the circuits implementing the protected logical gates, using a circuit-level error model. Furthermore, we analyze two different approaches to implement a fault-tolerant Toffoli gate on repetition cat qubits. These numerical simulations indicate that very low logical error rates could be achieved with a reasonable resource overhead, and with parameters that are within the reach of near-term circuit QED experiments.
We present a 1D repetition code based on the so-called cat qubits as a viable approach toward hardwareefficient universal and fault-tolerant quantum computation.The cat qubits that are stabilized by a twophoton driven-dissipative process exhibit a tunable noise bias where the effective bit-flip errors are exponentially suppressed with the average number of photons.We propose a realization of a set of gates on the cat qubits that preserve such a noise bias.Combining these base qubit operations, we build, at the level of the repetition cat qubit, a universal set of fully protected logical gates.This set includes single-qubit preparations and measurements, NOT, controlled-NOT, and controlled-controlled-NOT (Toffoli) gates.Remarkably, this construction avoids the costly magic state preparation, distillation, and injection.Finally, all required operations on the cat qubits could be performed with slight modifications of existing experimental setups.
Bosonic cat qubits stabilized by two-photon driven dissipation benefit from exponential suppression of bit-flip errors and an extensive set of gates preserving this protection. These properties make them promising building blocks of a hardware-efficient and fault-tolerant quantum processor. In this paper, we propose a performance optimization of the repetition cat code architecture using fast but noisy CNOT gates for stabilizer measurements. This optimization leads to high thresholds for the physical figure of merit, given as the ratio between intrinsic single-photon loss rate of the bosonic mode and the engineered two-photon loss rate, as well as an improved scaling below threshold of the required overhead, to reach an expected level of logical error rate. Relying on the specific error models for cat qubit operations, this optimization exploits fast parity measurements, using accelerated low-fidelity CNOT gates, combined with fast ancilla parity-check qubits. The significant enhancement in the performance is explained by: 1- the highly asymmetric error model of cat qubit CNOT gates with a major component on control (ancilla) qubits, and 2- the robustness of the repetition cat code error correction performance in presence of the leakage induced by fast operations. In order to demonstrate these performances, we develop a method to sample the repetition code under circuit-level noise that also takes into account cat qubit state leakage.
Qubits with strongly biased noise, in which phase-flip errors are orders of magnitude more frequent than bit-flips, arise both naturally, as in electron and nuclear spins, and by engineering, as in stabilized cat qubits. This noise structure holds the promise of reducing the daunting hardware overhead of fault-tolerant quantum computing, but exploiting it requires physical operations that do not convert frequent phase-flips into rare bit-flips. In this review, we analyze the most prominent fault-tolerant protocols for biased-noise qubits, organized according to the available set of such bias-preserving operations. When this set is restricted to the CZ gate together with preparation and measurement in the X basis, we show that the complexity of the required syndrome extraction gadgets essentially cancels the benefit of the noise bias: at experimentally relevant error rates, one may as well ignore the bias and rely on standard error correction designed for depolarizing noise. The situation changes drastically when a bias-preserving CX gate is available: the hierarchy of errors can then be reflected in the structure of the code, with frequent phase-flips corrected by a dedicated high-threshold code and rare bit-flips by concatenation with a high-rate code. The same hierarchy also enables hardware-efficient preparation of magic states. Finally, as a bias-preserving CX is forbidden in naturally biased platforms and challenging in engineered ones, we present a measurement-based architecture in which a high-fidelity quantum non-demolition readout of multi-qubit Pauli Z operators takes its place, extending these overhead reductions to a much broader range of physical platforms.
To solve problems of practical importance1,2, quantum computers probably need to incorporate quantum error correction, in which a logical qubit is redundantly encoded in many noisy physical qubits3–5. The large physical-qubit overhead associated with error correction motivates the search for more hardware-efficient approaches6–18. Here, using a superconducting quantum circuit19, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d = 5 (ref. 10). A stabilizing circuit passively protects cat qubits against bit flips20–24. The repetition code, using ancilla transmons for syndrome measurement, corrects cat qubit phase flips. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below the threshold. The logical bit-flip error is suppressed with increasing cat qubit mean photon number, enabled by our realization of a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the distance-5 code. Despite the increased number of fault locations of the distance-5 code, the high degree of noise bias preserved during error correction enables comparable performance. These results, where the intrinsic error suppression of the bosonic encodings enables us to use a hardware-efficient outer error-correcting code, indicate that concatenated bosonic codes can be a compelling model for reaching fault-tolerant quantum computation. Bosonic qubits can be engineered to feature intrinsic protection against certain kinds of errors, which makes quantum error correction across many bosonic qubits possible with less overhead.
Cat qubits provide appealing building blocks for quantum computing. They exhibit a tunable noise bias yielding an exponential suppression of bit flips with the average photon number and a protection against the remaining phase errors can be ensured by a simple repetition code. We here quantify the cost of a repetition code and provide valuable guidance for the choice of a large scale architecture using cat qubits by realizing a performance analysis based on the computation of discrete logarithms on an elliptic curve with Shor's algorithm. By focusing on a 2D grid of cat qubits with neighboring connectivity, we propose to implement 2-qubit gates via lattice surgery and Toffoli gates with off-line fault-tolerant preparation of magic states through projective measurements and subsequent gate teleportations. All-to-all connectivity between logical qubits is ensured by routing qubits. Assuming a ratio between single- and two-photon losses of 10^{-5} and a cycle time of 500 ns, we show concretely that such an architecture can compute a 256-bit elliptic curve logarithm in 9 h with 126 133 cat qubits and on average 19 photons by cat state. We give the details of the realization of Shor's algorithm so that the proposed performance analysis can be easily reused to guide the choice of architecture for others platforms.
Stabilized cat qubits that possess biased noise channel with bit-flip errors exponentially smaller than phase-flip errors. Together with a set of bias-preserving (BP) gates, cat qubits are a promising candidate for realizing hardware efficient quantum error correction and fault-tolerant quantum computing. Compared to dissipatively stabilized cat qubits, the Kerr cat qubits can in principle support faster gate operations with higher gate fidelity, benefiting from the large energy gap that protects the code space. However, the leakage of the Kerr cats can increase the minor type of errors and compromise the noise bias. Both the fast implementation of gates and the interaction with environment can lead to such detrimental leakage if no sophisticated controls are applied. In this work, we introduce new fine-control techniques to overcome the above obstacles for Kerr cat qubits. To suppress the gate leakage, we use the derivative-based transition suppression technique to design derivative-based controls for the Kerr BP gates. We show that the fine-controlled gates can simultaneously have high gate fidelity and high noise bias and when applied to concatenated quantum error correction, can not only improve the logical error rate but also reduce resource overhead. To suppress the environment-induced leakage, we introduce colored single-photon dissipation, which can continuously cool the Kerr cats and suppress the minor errors while not enhancing the major errors.