The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 − 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.
The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 − 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.
Superconducting electronics based on Josephson junctions are used to sense and process electronic signals with minimal loss; however, they are ultrasensitive to magnetic fields, limited in their amplification capabilities, and difficult to manufacture. We have developed a 3-terminal, nanowire-based superconducting electrothermal device which has no Josephson junctions. This device, which we call the nanocryotron, can be patterned from a single thin film of superconducting material with conventional electron-beam lithography. The nanocryotron has a demonstrated gain of >20, can drive impedances of 100 kΩ, and operates in typical ambient magnetic fields. We have additionally applied it both as a digital logic element in a half-adder circuit, and as a digital amplifier for superconducting nanowire single-photon detectors pulses. The nanocryotron has immediate applications in classical and quantum communications, photon sensing, and astronomy, and its input characteristics are suitable for integration with existing superconducting technologies.
The observation of the gate-controlled supercurrent (GCS) effect in superconducting nanostructures initiated major research efforts toward the realisation of superconducting-based computing architectures. Here we introduce a universal logic circuit that can be a promising superconducting building block of classical hybrid supercomputers. We demonstrate a functionally complete set of logic gates by realising the AND, OR, NOT and COPY gates. The general layout and scalability of our device, combined with recent experiments demonstrating fast switching and small voltage signals, make it a functional candidate in superconducting electronics. Our device enables the realization of all classical logic gates and the half-adder combinational logic circuit using at most three nanowires, each uniquely configured with two side-gate electrodes.
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.
We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10−4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.
Scaling photonic quantum-information platforms requires arrays of superconducting nanowire single-photon detectors (SNSPDs) for feedforward control, in which optical operations are conditioned on Bell-state measurements relying on photon-coincidence detections. On-chip superconducting cryotron electronics, performing logic on detector outputs and driving optical modulators, could reduce latency and room-temperature interconnect complexity for feedforward schemes. To date, no cryotron circuits designed for this purpose have been demonstrated. We demonstrate a bias-programmable logic gate based on three nanocryotrons (nTrons) that implements selectable AND (coincidence), XOR (odd-parity), and OR functions. It operates on two electrical pulses at 4.2 K, with bit-error rates below 10−3, bias margins up to ±21.7%, and operation extending to 25 MHz over narrower bias windows. It performs coincidence and odd-parity detection on two SNSPDs' outputs with bit-error rates below 3.2×10−2. As proof-of-concept, we show that nTrons can drive capacitive loads up to 1.15 V, potentially enabling compatibility with electro-optic modulators in feedforward schemes.
Superconducting electronics have emerged as a promising platform for advanced information processing, offering unique opportunities for on chip computation and signal manipulation at cryogenic temperatures. These devices hold particular potential in applications ranging from quantum computing to high sensitivity magnetic sensing, where integrated logic and scalable circuit architectures are essential for performing complex computational and signal-processing tasks. In this work, we present a dual-input multilayered heater nanocryotron (hTron) that introduces both multi input functionality and reconfigurable logic capability within a single device. This capability represents a step forward toward realizing more complex computational architectures. In addition, we demonstrate that these devices can, in principle, drive one another and potentially be integrated on a larger scale. Furthermore, the inherent reconfigurability of the demonstrated device allows for dynamic switching between logic operations without requiring additional components which reduces circuit area and simplifies cryogenic and biasing requirements, making the design highly suitable for scalable superconducting computing systems.