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arXiv:2211.05300 · Quantum Science and Technology

Modularized and scalable compilation for double quantum dot quantum computing

Run-Hong He, Xusheng Xu, Mark Byrd, Zhao-Ming Wang

Published Sep 28, 2023• 1 citation
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Abstract

Abstract Any quantum program on a realistic quantum device must be compiled into an executable form while taking into account the underlying hardware constraints. Stringent restrictions on architecture and control imposed by physical platforms make this very challenging. In this paper, based on the quantum variational algorithm, we propose a novel scheme to train an Ansatz circuit and realize high-fidelity compilation of a set of universal quantum gates for singlet-triplet qubits in semiconductor double quantum dots, a fairly heavily constrained system. Furthermore, we propose a scalable architecture for a modular implementation of quantum programs in this constrained systems and validate its performance with two representative demonstrations, the Grover’s algorithm for the database searching (static compilation) and a variant of variational quantum eigensolver for the Max-Cut optimization (dynamic compilation). Our methods are potentially applicable to a wide range of physical devices. This work constitutes an important stepping-stone for exploiting the potential for advanced and complicated quantum algorithms on near-term devices.

DOI
10.1088/2058-9565/acfe38

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Abstract Implementing quantum algorithms on realistic devices requires translating high-level global operations into sequences of hardware-native logic gates, a process known as quantum compiling. Physical limitations, such as constraints in connectivity and gate alphabets, often result in unacceptable implementation costs. To enable successful near-term applications, it is crucial to optimize compilation by exploiting the capabilities of existing hardware. Here we implement a resource-efficient construction for a quantum version of AND logic that can reduce the compilation overhead, enabling the execution of key quantum circuits. On a high-scalability superconducting quantum processor, we demonstrate low-depth synthesis of high-fidelity generalized Toffoli gates with up to 8 qubits and Grover’s search algorithm in a search space of up to 64 entries. Our experimental demonstration illustrates a scalable and widely applicable approach to implementing quantum algorithms, bringing more meaningful quantum applications on noisy devices within reach.
Semiconductor quantum dots provide a promising platform for spin qubit manipulation and quantum logic gate implementation, which are essential for scalable quantum computing architectures. In this work we utilize a variational quantum compiling algorithm to design efficient three-qubit gates using a time-independent Hamiltonian composed of only physical interaction terms. The resulting gates, including the Toffoli and Fredkin gates, demonstrate high fidelity and robustness against both coherent and incoherent noise sources, including charge and nuclear spin noise. This method is applicable to a wide range of physical systems, such as superconducting qubits and trapped ions, paving the way for more resilient and universal quantum computing architectures.
A quantum compiler is required to run a quantum circuit on a quantum computer, similar to how classical compilers are required to run programs on classical computers. Spin qubits are a promising candidate for scalable quantum computers. General-purpose quantum compilers can be used for spin qubit devices, however they do not consider additional constraints imposed due to Double-Quantum-Dot (DQD) readout. For DQD readout, when a qubit in an algorithm is measured, the compiler must remap and re-route it to be adjacent to a special-purpose readout qubit, which is preserved in a known state. Moreover, this should be done in a way that minimizes overhead and maximizes the fidelity, in particular, due to noise in the readout process. This work formulates readout constraints to extend SMT (Satisfiability Modulo Theory)-based layout synthesis techniques proposed in [1] to spin qubit architectures. We define a metric, readout depth, to quantify the overheads incurred. Preliminary results, obtained from benchmarking GHZ and variational quantum eigensolver circuits on architectures with grid topologies, highlight the algorithmic tradeoffs that arise. We expect ongoing work on scaling up the methods to a larger set of algorithms will help inform the decisions of spin qubit hardware designers.
Quantum circuit compilation is a critical step in realizing quantum algorithms on real quantum hardware. Traditional compilation methods often employ static optimization strategies, neglecting the unique constraints and characteristics of the target quantum device. This paper introduces a novel adaptive quantum circuit compilation framework designed to dynamically adjust circuit designs based on hardware-specific information, aiming to minimize gate count and, consequently, error rates. The core of the framework lies in integrating a hardware simulator directly within the compilation process. This allows the compiler to evaluate the performance of various circuit designs—considering factors like qubit connectivity, gate fidelity, and decoherence models—before committing to a final layout. The proposed approach represents a shift from static to adaptive optimization, providing a more nuanced and effective strategy for translating quantum algorithms into executable code on diverse quantum hardware platforms. This research demonstrates a significant potential improvement in quantum circuit efficiency and fidelity, addressing a key bottleneck in the advancement of quantum computing.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.512.512.5 for N=12N=12N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30N=30N=30 reveal that the optimal depth dmaxd_{\rm max}dmax​ to achieve maximal overall fidelity is independent of system size NNN, suggesting the scalability of our method for large quantum devices in terms of quantum resources.