The increasing capabilities of quantum computing hardware and the challenge of realizing deep quantum circuits require fully automated and efficient tools for compiling quantum circuits. To express arbitrary circuits in a sequence of native gates specific to the quantum computer architecture, it is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the quantum circuit framework Pytket. The performance was evaluated for a wide range of quantum circuits and the results show that the gate counts can be reduced by factors up to 5.1 compared to standard Pytket and up to 2.2 compared to standard Qiskit compilation.
The increasing capabilities of quantum computing hardware and the challenge of realizing deep quantum circuits require fully automated and efficient tools for compiling quantum circuits. To express arbitrary circuits in a sequence of native gates specific to the quantum computer architecture, it is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the quantum circuit framework Pytket. The performance was evaluated for a wide range of quantum circuits and the results show that the gate counts can be reduced by factors up to 5.1 compared to standard Pytket and up to 2.2 compared to standard Qiskit compilation.
The Quantum Charge Coupled Device (QCCD) architecture is a promising pathway toward scalable quantum computation in trapped-ion quantum computers. Devices using this architecture rely on efficient ion shuttling between memory and processing zones to execute quantum circuits. Hardware for trapped-ion quantum computers with multiple different zones is already being developed, but without proper compilation support, there is a risk that we will not be able to use their full potential. Recent approaches to shuttling algorithms have primarily focused on small architectures or devices with a single processing zone. In this work, we propose to extend these algorithms to large grid-type systems with multiple processing zones embedded in the memory zone. For that, a two-step solution is described: first, partitioning quantum circuits to determine where each gate is executed, and second, adapting a publicly available shuttling algorithm for architectures with a single processing zone to handle the increased complexity of multi-zone systems. Empirical evaluations demonstrate the method's effectiveness across a range of grid-type architectures, showing that additional processing zones can significantly reduce quantum circuit execution time. With that, we provide a foundation for the compilation of shuttling-based trapped-ion quantum computers with multiple processing zones. An open-source implementation of the proposed approach is available at https://github.com/cda-tum/mqt-ion-shuttler.
Current trapped-ion quantum computer architectures based on segmented traps utilize shuttling operations to establish connectivity between multiple sub-registers within one quantum processing unit. Complex trap architectures, including racetrack loops and junctions, offer prospects for increased scalability and have been successfully built and demonstrated. As hardware capabilities evolve, the need arises for additional automated software layers within the control stack for managing qubit routing. We present the automated generation of shuttling schedules for a branched ID architecture within a shuttling compiler that requires the integration of junctions. This not only provides the means for leveraging future new hardware advances, but also allows guiding the development of future architecture via resource estimation. Testing a wide range of quantum circuits, the junction-enabled shuttling compiler is able to reduce the necessary operations by a factor > 50 for translations and > 20 for separation/merge as compared to a linear architecture.
Shuttling-based trapped-ion quantum computers (QCCD) rank among the most mature hardware platforms. Existing and envisaged devices exhibit architectural differences in terms of register layout and connectivity. Platform-specific compilers are required to translate quantum circuits into resource-optimized hardware-level command chains. Hardware platforms and compiler software stacks are mostly developed independently of one another by different research communities. This work aims to bridge these communities by abstracting QCCD architectures and native operations, enabling computer scientists to address compilation problems using generic methods without requiring a deep background in the physical operating principles of the platform. The resulting design space is organized into a small set of architectural archetypes, each posing its own compilation problem. We then select and apply compilation methods to one- and two-dimensional QCCD architectures, finding that the routing overhead scales approximately cubically with the number of qubits for the one-dimensional architecture and approximately quadratically for the two-dimensional one. Extending this to compilation with a quantum error-correction layer reveals additional differences and similarities between the physical and logical levels. We conclude that co-design is a requirement rather than an option, and this work provides the vocabulary, archetypes, and compilation abstraction it needs.
Trapped-ion quantum computer hardware is scaling to larger qubit numbers, but the computational capabilities of these devices remain largely unknown. From an abstract computer-science perspective, we address this problem in a two-step approach: First, we categorize levels of qubit connectivity for a processor based on ion-shuttling and individual ion addressing. Second, we apply computer-science techniques to develop optimized compilers that map arbitrary algorithms to sequences of ion-register reconfiguration and gate operations. We present compilers for 1D and 2D architectures, optimizing cost functions such as the qubit reconfiguration effort.
Transformers have gained popularity in machine learning due to their application in the field of natural language processing. They manipulate and process text efficiently, capturing long-range dependencies among data and performing the next word prediction. On the other hand, gate-based quantum computing is based on controlling the register of qubits in the quantum hardware by applying a sequence of gates, a process which can be interpreted as a low level text programming language. We develop a transformer model capable of transpiling quantum circuits from the qasm standard to other sets of gates native suited for a specific target quantum hardware, in our case the set for the trapped-ion quantum computers of IonQ. The feasibility of a translation up to five qubits is demonstrated with a percentage of correctly transpiled target circuits equal or superior to 99.98%. Regardless the depth of the register and the number of gates applied, we prove that the complexity of the transformer model scales, in the worst case scenario, with a polynomial trend by increasing the depth of the register and the length of the circuit, allowing models with a higher number of parameters to be efficiently trained on HPC infrastructures.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.