Experiments conducted on open-access cloud-based IBM Quantum devices are presented for characterizing their fault tolerance using [4,2,2]-encoded gate sequences. Up to 100 logical gates are activated in the Ibmq_Bogota and Ibmq_Santiago devices and we found that a [4,2,2] code’s logical gate set may be deemed fault-tolerant for gate sequences larger than 10 gates. However, certain circuits did not satisfy the fault tolerance criterion. In some cases the encoded-gate sequences show a high error rate that is lower bounded at ≈ 0.1, whereby the error inherent in these circuits cannot be mitigated by classical post-selection. A comparison of the experimental results to a simple error model reveal that the dominant gate errors cannot be readily represented by the popular Pauli error model. Finally, it is most accurate to assess the fault tolerance criterion when the circuits tested are restricted to those that give rise to an output state with a low dimension.
Experiments conducted on open-access cloud-based IBM Quantum devices are presented for characterizing their fault tolerance using [4,2,2]-encoded gate sequences. Up to 100 logical gates are activated in the Ibmq_Bogota and Ibmq_Santiago devices and we found that a [4,2,2] code’s logical gate set may be deemed fault-tolerant for gate sequences larger than 10 gates. However, certain circuits did not satisfy the fault tolerance criterion. In some cases the encoded-gate sequences show a high error rate that is lower bounded at ≈ 0.1, whereby the error inherent in these circuits cannot be mitigated by classical post-selection. A comparison of the experimental results to a simple error model reveal that the dominant gate errors cannot be readily represented by the popular Pauli error model. Finally, it is most accurate to assess the fault tolerance criterion when the circuits tested are restricted to those that give rise to an output state with a low dimension.
Quantum computers hold the promise to solve some hard problems that are intractable for even the most powerful current supercomputers. One of the most famous examples is Shor's algorithm for factorizing large numbers, which has exponential speedup compared to its best classical counterparts. However, running such an algorithm will require to build a large-scale quantum computer consisting of thousands or even millions of qubits that include quantum error correction (QEC) and fault-tolerant (FT) mechanisms. Quantum computing is already a reality with the so-called Noisy Intermediate-Scale Quantum (NISQ) processors, some of them available in the cloud. Noisy refers to the imperfect control over the qubits and intermediate-scale to the relatively low number of quits (from fifty to a few hundred). Although current and near-term quantum devices will not have enough qubits for implementing large and fully corrected quantum computations, the use of small quantum error correction codes may extend the computation lifetime of NISQ devices. In this context and as a first step, it is important to test and demonstrate the fault-tolerance of these QEC codes. In this thesis, we explore the fault-tolerance of two small quantum correction codes that are good candidates to be applied to NISQ processors, the [[4,2,2]] code and the [[7,1,3]] Steane code. To this purpose, by following the FT criterion prosed by Daniel Gottesman in 2016, we tested both codes using two simulators, the stabilizer formalism simulator that includes quite simple error models and a full density matrix simulator called quantumsim, which includes more realistic noise. The simulations are performed under reasonable noise parameter values. For the [[4,2,2]] code, 235 circuits are tested based on the two simulators. The results show that in the stabilizer formalism simulation, the FT criterion is satised for all circuits, while not fully satisfied in the full density matrix simulation. For the [[7,1,3]] Steane code, we use a parallel-flag error correction implementation which is tested using the full density matrix simulator. Our results show that without applying any QEC cycle, for all circuits (84 circuits for 1 logical qubit simulation and 452 circuits for 2 logical qubits simulation), the error rate of the encoded circuits is lower than the unencoded ones. Adding a quantum error correction (QEC) cycle will in general increase the error rate of the computation.
Quantum error correction is necessary to perform large-scale quantum computations in the presence of noise and decoherence. As a result, several aspects of quantum error correction have already been explored. These have been primarily studies of quantum memory[1, 2], an important first step towards quantum computation, where the objective is to increase the lifetime of the encoded quantum information. Additionally, several works have explored the implementation of logical gates[3-5]. In this work we study a next step - fault-tolerantly implementing quantum circuits. We choose the [[4,1,2]] Bacon-Shor subsystem code, which has a particularly simple error-detection circuit. Through both numerics and site-counting arguments, we compute pseudo-thresholds for the Pauli error rate p in a depolarizing noise model, below which the encoded circuits outperform the unencoded circuits. These pseudo-threshold values are shown to be as high as p=3% for short circuits, and p=0.6% for circuits of moderate depth. Additionally, we see that multiple rounds of stabilizer measurements give an improvement over performing a single round at the end. This provides a concrete suggestion for a small-scale fault-tolerant demonstration of a quantum algorithm that could be accessible with existing hardware.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Mid-circuit measurements used in quantum error correction are essential in the architecture of a fault-tolerant quantum computer, as they read out syndrome data and drive logic gates. Here, we use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic. First, we identify that idling errors occurring during readout periods are highly detrimental to a quantum memory. We demonstrate significant improvements to the memory by designing and implementing a low-depth syndrome extraction circuit. Second, we perform a stability experiment to investigate the type of failures that can occur during logic gates due to readout assignment errors. We find that the error rate of the stability experiment improves with additional stabilizer readout cycles, revealing a trade-off as additional stability comes at the expense of time over which the memory can decay. We corroborate our results using holistic device benchmarking and by comparison to numerical simulations. Finally, by varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates, with measurement noise playing a dominant role in logical gate performance. With rapid progress in quantum error correction, clear performance benchmarks are needed to assess readiness for fault tolerant operation. Here the authors report benchmarking and noise characterization in a superconducting quantum processor, identifying key factors that impact error-corrected logic.
Benchmarking physical devices and verifying logical algorithms are important tasks for scalable fault-tolerant quantum computing. Numerous protocols exist for benchmarking devices before running actual algorithms. In this work, we show that both physical and logical errors of fault-tolerant circuits can even be characterized in-situ using syndrome data. To achieve this, we map general fault-tolerant Clifford circuits to subsystem codes using the spacetime code formalism and develop a scheme for estimating Pauli noise in Clifford circuits using syndrome data. We give necessary and sufficient conditions for the learnability of physical and logical noise from given syndrome data, and show that we can accurately predict logical fidelities from the same data. Importantly, our approach requires only a polynomial sample size, even when the logical error rate is exponentially suppressed by the code distance, and thus gives an exponential advantage against methods that use only logical data such as direct fidelity estimation. We demonstrate the practical applicability of our methods in various scenarios using synthetic data as well as the experimental data from a recent demonstration of fault-tolerant circuits by Bluvstein et al. [Nature 626, 7997 (2024)]. Our methods provide an efficient, in-situ way of characterizing a fault-tolerant quantum computer to help gate calibration, improve decoding accuracy, and verify logical circuits.
Quantum error-detecting codes offer a near-term path for improving the performance of quantum simulations on noisy hardware. Using IBM's superconducting quantum computer ibm_boston, we show that partially fault-tolerant encoded quantum simulations of the Ising model in 1+1D and 2+1D outperform their unencoded counterparts in estimating local observables. To represent 42 logical qubits on the heavy-hex quantum processor, 21 blocks of the [[4, 2, 2]] Iceberg code and up to 136 physical qubits are used. By pairing fault-tolerant syndrome extraction with non-fault-tolerant logical operations, this scheme preserves many of the benefits of error detection while avoiding the overhead typically required for a fully fault-tolerant logical gate set. The encoding's square logical connectivity, together with the freedom to place logical qubits within each block, enables simulations of a 2D spatial lattice with lower circuit depth than the unencoded implementation requires. We introduce Observable-Ranked Postselection, a selective-filtering technique based on syndrome correlations that recovers reliable results without the prohibitive shot loss of full syndrome postselection. Under the cumulative effect of device errors, this encoding improves local-observable accuracy over the unencoded baseline by 2-6% at intermediate times in 1+1D simulations, growing with circuit depth to over 200% in 2+1D at the latest times studied.