When storing encoded qubits, if single faults can be corrected and double faults can be postselected against, logical errors occur due to at least three faults. At current noise rates, having to restart when two errors are detected prevents very long-term storage, but that should not be an issue for low-depth computations. We consider distance-four efficient encodings of multiple qubits into a modified planar patch of the 16-qubit surface code. We simulate postselected error correction for up to 12 000 rounds of parallel stabilizer measurements and subsequently estimate the cumulative probability of logical error for up to 12 encoded qubits. Our results demonstrate a combination of low logical error rate and low physical overhead. For example, the distance-four surface code, using postselection, accumulates 25 times less error than its distance-five counterpart. For six encoded qubits, a distance-four code using 25 qubits protects as well as the distance-five surface code using 246 qubits. Hence, distance-four codes, using postselection in a planar geometry, are qubit-efficient candidates for fault-tolerant, moderate-depth computations.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Quantum error correction (QEC) requires the execution of deep quantum circuits with large numbers of physical qubits to protect information against errors. Designing protocols that can reduce gate and space-time overheads of QEC is therefore crucial to enable more efficient QEC in near-term experiments. Multiqubit gates offer a natural path toward fast and low-depth stabilizer measurement circuits. However, they typically introduce high-weight correlated errors that can degrade the circuit-level distance, leading to slower scalings of the logical error probabilities. In this Letter, we show how to realize fast and efficient surface code stabilizer readout using only two singly controlled z gates acting simultaneously on two target qubits, i.e., two CZ_{2} gates-instead of four cz. We show that this scheme is fault tolerant and provide a blueprint for implementation in Rydberg atom arrays. We derive the time-optimal pulses implementing the gates and perform extensive QEC numerical simulations with Rydberg decay errors. Compared to the standard protocol using four cz gates, our scheme is faster, uses fewer gates, and crucially maintains fault tolerance with comparable logical error probabilities. Fault-tolerant generalizations of this scheme to biased and erasure-dominant noise models, as well as to other QEC codes such as quantum Low-Density Parity-Check codes, are also discussed.
The surface code is the leading candidate for fault-tolerant quantum computation owing to its planar nearest-neighbor connectivity, high threshold, and efficient decoding, but its low encoding rate demands on the order of a thousand physical qubits per logical qubit in the teraquop regime. Yoked surface codes improve the density by a factor of two or three by concatenating a high-density parity check code on top of the surface code while retaining planar nearest-neighbor connectivity. In this work, we generalize this idea to multiple levels of concatenation and introduce multi-yoked surface codes. Our construction rests on two new ingredients. First, we propose a family of outer codes called chain codes, built by chaining copies of a seed code that detects the block errors of the code one level below; the resulting codes use all logical qubits of the lower level and achieve a high encoding rate within a few concatenation levels. Second, we design a patch allocation in which movable workspaces perform the yoking checks by lattice surgery with a hierarchy of yoking intervals, so that lower-level checks are performed frequently while higher-level checks are performed less often, which avoids the long yoking intervals that a single large-distance outer code would require. As a benchmark, we construct a three-yoked surface code with a
[[256,166,8]] outer code and evaluate it numerically under the SI1000 noise model using soft information from the surface code decoder. The logical error rate is suppressed exponentially in the inner code distance, and in the teraquop regime the three-yoked surface code is about 4 to 4.5
× denser than the unyoked surface code.
Abstract The accumulation of physical errors 1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction 4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm 5 . We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes 6 . Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code 7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length- n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.
The planar surface code protects quantum information robustly but pays for its two-dimensional layout with an encoding rate that vanishes as the distance grows, so fault-tolerant memories require hundreds to thousands of physical qubits per logical qubit. A recent proposal constructs modular hyperbolic surface and color codes by partitioning a quantum processor into flat Euclidean modules and wiring sparse, static boundary connections between them, yielding semi-hyperbolic codes with constant encoding rate [1,4]. In this paper we provide an independent, fully explicit quantitative analysis of that proposal. Taking the reported parameters — encoding rate
k/n=1/16 and distance
d≥22 — as inputs, we compute that a twelve-logical-qubit modular memory requires
nmod=192 physical qubits, versus
11100 data qubits for twelve distance-
22 rotated surface-code patches, a raw overhead reduction of
57.8×; the reduction remains
≥30× even if the true modular implementation uses up to
370 physical qubits. We further develop a seam-noise mixture model and compute the seam-error budget under which the modular advantage survives: with a seam fraction
f=0.1443, seam links may carry up to
γ≈2.5× the intra-module error rate before a tenfold advantage at matched distance is exhausted. We compare against the
[[288,12,18]] bivariate bicycle code (
1.5× fewer qubits for the modular code, at strictly larger distance) and situate the proposal within the low-overhead QEC landscape. All arithmetic is shown step by step; all projections are labeled with stated assumptions. ## 1. Introduction Quantum error correction (QEC) is the accepted route to fault-tolerant quantum computation, but the leading practical scheme — the planar surface code — has an encoding rate
k/n that tends to zero as the code distance
d grows. For a target logical error rate, the required physical-to-logical qubit ratio grows roughly quadra Full text and updates: papers.qnfo.org/papers/low-overhead-quantum-error-correction-with-boundary-connected-planar-modules-a-r/
We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.