The implementation of large-scale fault-tolerant quantum computers calls for the integration of millions of physical qubits with very low error rates. This outstanding engineering challenge may benefit from emerging qubits that are protected from dominating noise sources in the qubits' environment. In addition to different noise reduction techniques, protective approaches typically encode qubits in global or local decoherence-free subspaces, or in dynamical sweet spots of driven systems. We exemplify such protected qubits by reviewing the state-of-art in protected solid-state qubits based on semiconductors, superconductors, and hybrid devices.
The implementation of large-scale fault-tolerant quantum computers calls for the integration of millions of physical qubits with very low error rates. This outstanding engineering challenge may benefit from emerging qubits that are protected from dominating noise sources in the qubits' environment. In addition to different noise reduction techniques, protective approaches typically encode qubits in global or local decoherence-free subspaces, or in dynamical sweet spots of driven systems. We exemplify such protected qubits by reviewing the state-of-art in protected solid-state qubits based on semiconductors, superconductors, and hybrid devices.
Hybrid semiconductor-superconductor qubits have recently emerged as a promising alternative to traditional platforms, combining material advantages with device-level tunability. A defining feature is their gate-tunable Josephson coupling, enabling superconducting qubit architectures with full electric-field control and offering a path toward scalable, low-crosstalk quantum processors. This approach seeks to merge benefits of superconducting and semiconductor qubits, for instance by encoding quantum information in the spin of a quasiparticle occupying an Andreev bound state, thus combining long coherence times with fast, flexible control. Progress has accelerated through bottom-up engineering of Andreev states in coupled quantum dot arrays, leading to architectures such as minimal Kitaev chains hosting Majorana zero modes. In parallel, Hamiltonian-protected designs aim to enhance resilience against local noise and decoherence by exploiting superconducting phase dynamics and discrete charge or flux degrees of freedom. This article reviews recent theoretical and experimental advances in hybrid qubits, providing an overview of physical mechanisms, device implementations, and emerging architectures, with emphasis on their potential for (topologically) protected quantum information processing. While many designs remain at proof-of-concept stage, rapid progress suggests practical demonstrations may soon be achievable.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.
In quantum computing, symmetry plays a central role in protecting qubits from errors. This work develops an efficient approach to creating decoherence-free subspaces for logical qubits, by optimally transferring the states of physical qubits via concatenated dynamical decoupling. This method bears a distinct superiority for many-qubit systems, owing to its polynomial speedup over previous approaches, which makes it promising for generating a higher-dimensional decoherence-free subspace to encode more protected logical qubits for fault-tolerant quantum computation.
The development of quantum Josephson circuits has created a strong expectation for reliable processing of quantum information. While this progress has already led to various proof-of-principle experiments on small-scale quantum systems, a major scaling step is required towards many-qubit protocols. Fault-tolerant computation with protected logical qubits usually comes at the expense of a significant overhead in the hardware. Each of the involved physical qubits still needs to satisfy the best achieved properties (coherence times, coupling strengths and tunability). Here, and in the aim of addressing alternative approaches to deal with these obstacles, I overview a series of recent theoretical proposals, and the experimental developments following these proposals, to enable a hardware-efficient paradigm for quantum memory protection and universal quantum computation.
The prospects for a utility-scale, fault-tolerant superconducting quantum computer have grown increasingly promising through demonstrations of quantum advantage and quantum error correction. The next breakthrough will likely be driven by processors at scale, with qubit counts exceeding tens of thousands. Achieving this scale presents a formidable challenge for current architectures, including limitations in chip footprint, cryogenic cooling capacity, and control complexity. One approach to alleviating these constraints is to make each qubit better, thereby reducing the redundancy required for error correction. Protected qubits provide a promising path in this direction by encoding quantum information into a decoherence-free subspace. This can be achieved through Hamiltonian engineering in superconducting circuits, with representative examples including the 0–π qubit, the cos(2φ) qubit, and the GKP qubit. In this thesis, we present the superconducting grid states qubit, or gridium, as a strong candidate for protected qubits. The gridium consists of a Cooper-quartet tunneling element shunted by a quantum phase slip element. We show that the gridium realizes a decoherence-free subspace within a single mode and can achieve strong protection using readily available superconducting circuit elements. We further demonstrate that its key components—Cooper-quartet tunneling and quantum phase slip—can be realized and engineered through appropriate circuit design, as illustrated with a prototype device. By applying Hamiltonian engineering, we construct three gridium devices with varying levels of protection. We show that the measured spectra are consistent with numerical simulations of the theoretical model. From these fits, we extract the corresponding wavefunctions and observe enhanced protection as the number of grids increases. To directly probe this protection, we measure the depolarization times of the devices while dynamically tuning the protection via flux control. Our best device exhibits T1 = 2.4 ms, comparable to state-of-the-art superconducting qubits. The gridium architecture presented in this thesis demonstrates strong potential for realizing fault-tolerant quantum processors based on protected qubits.
Semiconductor double quantum-dot hybrid qubits are promising candidates for high-fidelity quantum computing. However, their performance is limited by charge noise, which is ubiquitous in solid-state devices, and phonon-induced dephasing. Here we explore methods for improving the quantum operations of a hybrid qubit, using strong microwave driving to enable gate operations that are much faster than decoherence processes. Using numerical simulations and a theoretical method based on a cumulant expansion, we analyze qubit dynamics in the presence of 1/f charge noise, which forms the dominant decoherence mechanism in many solid-state devices. We show that, while strong-driving effects and charge noise both reduce the quantum gate fidelity, simple pulse-shaping techniques effectively suppress the strong-driving effects. Moreover, a broad AC sweet spot emerges when the detuning parameter and the tunneling coupling are driven simultaneously. Taking into account phonon-mediated noise, we find that it should be possible to achieve ${X}_{\ensuremath{\pi}}$ gates with fidelities higher than 99.9.