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arXiv:2108.02322

Architectural considerations in the design of a third-generation superconducting quantum annealing processor

Kelly Boothby, Colin Enderud, Trevor M. Lanting, Reza Molavi, Nicholas Tsai, Mark H. Volkmann, Fabio Altomare, M. H. S. Amin, Michael C. Babcock, A. J. Berkley, Catia Baron, Martin Boschnak, Holly Christiani, Sara Ejtemaee, Bram Evert, Matthew Gullen, Markus Hager, R. Harris, Emile Hoskinson, Jeremy Hilton, Kais Jooya, Huang, Ann, Mark W. Johnson, Andrew D. King, E. Ladizinsky, Ryan Li, Allison MacDonald, Teresa Medina Fernandez, Neufeld, Richard, Mana Norouzpour, Travis Oh, Isil Ozfidan, P. Paddon, I. Perminov, Gabriel Poulin-Lamarre, Prescott, Thomas, Jack Raymond, Reis, Mauricio, Chris C. Rich, Aidan Roy, Hossein Sadeghi Esfahani, Yuki Sato, Ben Sheldan, Anatoly Yu. Smirnov, Loren J. Swenson, Jed D. Whittaker, Jason J. Yao, Yarovoy, Alexander, P. Bunyk

Published Aug 5, 2021• 13 citations
arXivHTMLPDF

Abstract

Early generations of superconducting quantum annealing processors have provided a valuable platform for studying the performance of a scalable quantum computing technology. These studies have directly informed our approach to the design of the next-generation processor. Our design priorities for this generation include an increase in per-qubit connectivity, a problem Hamiltonian energy scale similar to previous generations, reduced Hamiltonian specification errors, and an increase in the processor scale that also leaves programming and readout times fixed or reduced. Here we discuss the specific innovations that resulted in a processor architecture that satisfies these design priorities.

DOI
10.48550/arxiv.2108.02322

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Early generations of superconducting quantum annealing processors have provided a valuable platform for studying the performance of a scalable quantum computing technology. These studies have directly informed our approach to the design of the next-generation processor. Our design priorities for this generation include an increase in per-qubit connectivity, a problem Hamiltonian energy scale similar to previous generations, reduced Hamiltonian specification errors, and an increase in the processor scale that also leaves programming and readout times fixed or reduced. Here we discuss the specific innovations that resulted in a processor architecture that satisfies these design priorities.
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More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.
More physical qubits and qubit connections integrated on a superconducting quantum processor can improve the ability to execute quantum programs, but on the other hand, they might increase the probability of frequency collisions. Considering a performance and frequency collisions trade-off, it is a feasible method to optimize processor architecture aiming at running specific quantum programs. To this end, we propose a method for designing superconducting quantum processor architectures for the purpose of running specific quantum programs. Different from existing methods, our method is mainly based on graph theory to optimize processor architecture design. First, we convert the trade-off problem into the optimization of the distance between two points as well as the maximum degree in the processor architecture graph. Second, we consider the actual physical routing constraints and build a mathematical model for the optimization problem. Finally, we propose an automatic processor architecture design flow based on the mathematical model, which is implemented with an improved genetic algorithm. To show the effectiveness of our method, we selected sixteen quantum programs with different qubit numbers and different functions for comparison. Simulation results show that the architecture schemes of our method outperform IBM’s general-purpose square lattice architecture schemes. Compared to the general-purpose architecture schemes, the architecture schemes of our method have an average performance improvement of 15.61% and a minimum reduction of 21.33% in the probability of frequency collisions. Furthermore, in most of the selected quantum programs, our architecture schemes perform better than the eff-5-freq’s architecture schemes, with an average 6.58% improvement in performance and a minimum 6.45% reduction in the probability of frequency collisions. Therefore, our method can provide superconducting quantum processor architecture design with better performance and lower probability of frequency collisions for quantum programs.