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arXiv:2107.11981

An exchange-based surface-code quantum computer architecture in silicon

Charles D. Hill, Muhammad Usman, Lloyd C. L. Hollenberg

Published Jul 26, 2021• 2 citations
arXivHTMLPDF

Abstract

Phosphorus donor spins in silicon offer a number of promising characteristics for the implementation of robust qubits. Amongst various concepts for scale-up, the shared-control concept takes advantage of 3D scanning tunnelling microscope (STM) fabrication techniques to minimise the number of control lines, allowing the donors to be placed at the pitch limit of $\geq$30 nm, enabling dipole interactions. A fundamental challenge is to exploit the faster exchange interaction, however, the donor spacings required are typically 15 nm or less, and the exchange interaction is notoriously sensitive to lattice site variations in donor placement. This work presents a proposal for a fast exchange-based surface-code quantum computer architecture which explicitly addresses both donor placement imprecision commensurate with the atomic-precision fabrication techniques and the stringent qubit pitch requirements. The effective pitch is extended by incorporation of an intermediate donor acting as an exchange-interaction switch. We consider both global control schemes and a scheduled series of operations by designing GRAPE pulses for individual CNOTs based on coupling scenarios predicted by atomistic tight-binding simulations. The architecture is compatible with the existing fabrication capabilities and may serve as a blueprint for the experimental implementation of a full-scale fault-tolerant quantum computer based on donor impurities in silicon.

DOI
10.48550/arxiv.2107.11981

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Phosphorus donor spins in silicon offer a number of promising characteristics for the implementation of robust qubits. Amongst various concepts for scale-up, the shared-control concept takes advantage of 3D scanning tunnelling microscope (STM) fabrication techniques to minimise the number of control lines, allowing the donors to be placed at the pitch limit of ≥\geq≥30 nm, enabling dipole interactions. A fundamental challenge is to exploit the faster exchange interaction, however, the donor spacings required are typically 15 nm or less, and the exchange interaction is notoriously sensitive to lattice site variations in donor placement. This work presents a proposal for a fast exchange-based surface-code quantum computer architecture which explicitly addresses both donor placement imprecision commensurate with the atomic-precision fabrication techniques and the stringent qubit pitch requirements. The effective pitch is extended by incorporation of an intermediate donor acting as an exchange-interaction switch. We consider both global control schemes and a scheduled series of operations by designing GRAPE pulses for individual CNOTs based on coupling scenarios predicted by atomistic tight-binding simulations. The architecture is compatible with the existing fabrication capabilities and may serve as a blueprint for the experimental implementation of a full-scale fault-tolerant quantum computer based on donor impurities in silicon.
A scaled quantum computer with donor spins in silicon would benefit from a viable semiconductor framework and a strong inherent decoupling of the qubits from the noisy environment. Coupling neighboring spins via the natural exchange interaction according to current designs requires gate control structures with extremely small length scales. We present a silicon architecture where bismuth donors with long coherence times are coupled to electrons that can shuttle between adjacent quantum dots, thus relaxing the pitch requirements and allowing space between donors for classical control devices. An adiabatic SWAP operation within each donor/dot pair solves the scalability issues intrinsic to exchange-based two-qubit gates, as it does not rely on subnanometer precision in donor placement and is robust against noise in the control fields. We use this SWAP together with well established global microwave Rabi pulses and parallel electron shuttling to construct a surface code that needs minimal, feasible local control.
The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topological quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel-posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically separated control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited.
Donor-based spin qubit offers a promising silicon quantum computing route for building large-scale qubit arrays, attributed to its long coherence time and advancements in nanoscale donor placement. However, the state-of-the-art device designs face scalability challenges, notably in achieving tunable two-qubit coupling and ensuring qubit addressability. Here, we propose a surface-code-compatible architecture, where each module has both tunable two-qubit gates and addressable single-qubit gates by introducing only a single extra donor in a pair of donors. We found that to compromise between the requirement of tunability and that of addressability, an asymmetric scheme is necessary. In this scheme, the introduced extra donor is strongly tunnel-coupled to one of the donor spin qubits for addressable single-qubit operation, while being more weakly coupled to the other to ensure the turning on and off of the two-qubit operation. The fidelity of single-qubit and two-qubit gates can exceed the fault-tolerant threshold in our design. Additionally, the asymmetric scheme effectively mitigates valley oscillations, allowing for engineering precision tolerances up to a few nanometers. Thus, our proposed scheme presents a promising prototype for large-scale, fault-tolerant, donor-based spin quantum processors.
Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.Quantum computers will require a large network of coherent qubits, connected in a noise-resilient way. Tosi et al. present a design for a quantum processor based on electron-nuclear spins in silicon, with electrical control and coupling schemes that simplify qubit fabrication and operation.
Abstract Individual impurity atoms in silicon can make superb individual qubits, but it remains an immense challenge to build a multi-qubit processor: there is a basic conflict between nanometre separation desired for qubit–qubit interactions and the much larger scales that would enable control and addressing in a manufacturable and fault-tolerant architecture. Here we resolve this conflict by establishing the feasibility of surface code quantum computing using solid-state spins, or ‘data qubits’, that are widely separated from one another. We use a second set of ‘probe’ spins that are mechanically separate from the data qubits and move in and out of their proximity. The spin dipole–dipole interactions give rise to phase shifts; measuring a probe’s total phase reveals the collective parity of the data qubits along the probe’s path. Using a protocol that balances the systematic errors due to imperfect device fabrication, our detailed simulations show that substantial misalignments can be handled within fault-tolerant operations. We conclude that this simple ‘orbital probe’ architecture overcomes many of the difficulties facing solid-state quantum computing, while minimising the complexity and offering qubit densities that are several orders of magnitude greater than other systems.
A scalable quantum information processing architecture based on silicon metal-oxide-semiconductor technology is presented, combining quantum hardware elements from planar and 3D silicon-on-insulator technologies. This architecture is expressed in the ``unit cell'' approach, where tiling cells in two dimensions and allowing inter-cellular nearest-neighbour interactions makes the architecture compatible with the surface code for fault tolerant quantum computation. The architecture utilises global control methods, substantially reducing processor complexity with scale: Single-qubit control is achieved using globally applied spin-resonance techniques and two-qubit interactions are mediated by large quantum dots. Further, a solution to device variation is proposed through integration of electronics for individual trimming of quantum dot voltage references. Such a combined set of solutions addresses several major barriers to scaling quantum machines within completely silicon based architectures.