As the size and complexity of a quantum computer increases, quantum bit (qubit) characterization and gate optimization become complex and time-consuming tasks. Current calibration techniques require complicated and verbose measurements to tune up qubits and gates, which cannot easily expand to the large-scale quantum systems. We develop a concise and automatic calibration protocol to characterize qubits and optimize gates using QubiC, which is an open source FPGA (field-programmable gate array) based control and measurement system for superconducting quantum information processors. We propose mutli-dimensional loss-based optimization of single-qubit gates and full XY-plane measurement method for the two-qubit CNOT gate calibration. We demonstrate the QubiC automatic calibration protocols are capable of delivering high-fidelity gates on the state-of-the-art transmon-type processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit Clifford gate infidelities measured by randomized benchmarking are of $4.9(1.1) \times 10^{-4}$ and $1.4(3) \times 10^{-2}$, respectively.
As the size and complexity of a quantum computer increases, quantum bit (qubit) characterization and gate optimization become complex and time-consuming tasks. Current calibration techniques require complicated and verbose measurements to tune up qubits and gates, which cannot easily expand to the large-scale quantum systems. We develop a concise and automatic calibration protocol to characterize qubits and optimize gates using QubiC, which is an open source FPGA (field-programmable gate array) based control and measurement system for superconducting quantum information processors. We propose mutli-dimensional loss-based optimization of single-qubit gates and full XY-plane measurement method for the two-qubit CNOT gate calibration. We demonstrate the QubiC automatic calibration protocols are capable of delivering high-fidelity gates on the state-of-the-art transmon-type processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit Clifford gate infidelities measured by randomized benchmarking are of 4.9(1.1)×10−4 and 1.4(3)×10−2, respectively.
As the size and complexity of a quantum computer increases, quantum bit (qubit) characterization and gate optimization become complex and time-consuming tasks. Current calibration techniques require complicated and verbose measurements to tune up qubits and gates, which cannot easily expand to the large-scale quantum systems. We develop a concise and automatic calibration protocol to characterize qubits and optimize gates using QubiC , which is an open source FPGA (field-programmable gate array)-based control and measurement system for superconducting quantum information processors. We propose multi-dimensional loss-based optimization of single-qubit gates and full XY-plane measurement method for the two-qubit CNOT gate calibration. We demonstrate the QubiC automatic calibration protocols are capable of delivering high-fidelity gates on the state-of-the-art transmon-type processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit Clifford gate infidelities measured by randomized benchmarking are of 4.9(1.1) × 10 -4 and 1.4(3) × 10 -2 , respectively.
As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system level optimization. We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software. A prototype hardware module is assembled from several commercial off-the-shelf evaluation boards and in-house developed circuit boards. Gateware and software are designed to implement basic qubit control and measurement protocols. System functionality and performance are demonstrated by performing qubit chip characterization, gate optimization, and randomized benchmarking sequences on a superconducting quantum processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit process fidelities are measured to be 0.99800.0001 and 0.9480.004 by randomized benchmarking. With fast circuit sequence loading capability, the QubiC performs randomized compiling experiments efficiently and improves the feasibility of executing more complex algorithms.
Researchers manipulate and measure quantum processing units via the classical electronics control system. We developed an open-source FPGA-based quantum bit control system called QubiC for superconducting qubits. After years of qubit calibration and testing experience on QubiC 1.0, we recognized the need for mid-circuit measurement and feed-forward capabilities to implement advanced quantum algorithms, and upgraded the system to QubiC 2.0 on an AMD ZCU216 RFSoC evaluation board with all these enriched features. The system uses portable FPGA gateware with a simplified processor to handle commands on-the-fly. For design simplicity and straightforward scaling, we adopted a multi-core distributed architecture, assigning one processor core per qubit. The pulses combine the unique pulse envelope and carrier information specified in a command. Each pulse envelope is pre-stored in the FPGA's block RAMs, ensuring speed and reusability throughout the quantum circuit, while pulse parameters including amplitude, phase, and frequency can be updated from pulse to pulse. The software stack is developed in Python, running on both the FPGA's ARM core and a host computer via XML-RPC. Quantum circuits can be described in a high-level language supporting both pulse-level and native-gate-level programming with high-level control flow constructs, and are compiled into binary commands loaded into the FPGA. With QubiC 2.0, we achieved multi-FPGA synchronization and low-latency data communication, and demonstrated feed-forward experiments on conditional circuits. The system also serves as a platform for artificial intelligence and machine learning driven quantum control, such as FPGA-based real-time quantum state discrimination. The enhanced QubiC system provides researchers with powerful tools to explore and implement advanced quantum algorithms and applications.
As quantum systems expand in size and complexity, manual qubit characterization and gate optimization will be a non-scalable and time-consuming venture. Physical qubits have to be carefully calibrated because quantum processors are very sensitive to the external environment, with control hardware parameters slowly drifting during operation, affecting gate fidelity. Currently, existing calibration techniques require complex and lengthy measurements to independently control the different parameters of each gate and are unscalable to large quantum systems. Therefore, fully automated protocols with the desired functionalities are required to speed up the calibration process. This paper aims to propose single-qubit calibration of superconducting qubits under continuous weak measurements from a real physical experimental settings point of view. We propose a real-time optimal estimator of qubit states, which utilizes weak measurements and Bayesian optimization to find the optimal control pulses for gate design. Our numerical results demonstrate a significant reduction in the calibration process, obtaining a high gate fidelity. Using the proposed estimator we estimated the qubit state with and without measurement noise and the estimation error between the qubit state and the estimator state is less than 0.02. With this setup, we drive an approximated pi pulse with final fidelity of 0.9928. This shows that our proposed strategy is robust against the presence of measurement and environmental noise and can also be applicable for the calibration of many other quantum computation technologies.
Manipulating qubits and measuring quantum processors via quantum bit control systems is traditionally done using expensive, off-the-shelf commercial electronics setups. Previously, we have introduced QubiC, an open-source FPGA-based quantum bit control system developed at Lawrence Berkeley National Laboratory. After a few years of operating on the QubiC 1.0, we realized the urgent requirements on the mid-circuits measurement and feed forward to implement advanced quantum algorithms. This requirement led to engineering a novel QubiC 2.0 on top of the RFSoC technique, incorporating enriched features. The QubiC 2.0. presented in this manuscript is implemented on the Xilinx evaluation board ZCU216. We developed a portable FPGA gateware with a lean soft processor to handle the quantum commands on the fly. Further, we created a distributed architecture with multiple processors, with a one-to-one mapping between processors and qubits, creating a parallel qubit control and measurement. Like a regular CPU, these processors access pulse envelope commands with parameterized amplitude, phase, and frequency to generate pulse information on the FPGA to ensure the speed and reusability of the entire quantum circuit. The Python software layer abstracts the low-level gateware and provides the compiler, assembler, and remote procedure call for host-to-board communication. The compiled software runs on a Python runtime environment, interfacing with the low-level gateware and hardware connected to a Quantum Processing Unit, creating a full-stack quantum bit control system. We demonstrate the architecture and the broad capabilities of QubiC 2.0 with a simplified feed forward experiment on a conditional circuit.
Superconducting qubit parameters drift on sub-second timescales, motivating calibration and benchmarking techniques that can be executed on millisecond timescales. We demonstrate an on-FPGA workflow that co-locates pulse generation, data acquisition, analysis, and feed-forward, eliminating CPU round trips. Within this workflow, we introduce sparse-sampling and on-FPGA inference tools, including computationally efficient methods for estimation of exponential and sine-like response functions, as well as on-FPGA implementations of Nelder-Mead optimization and golden-section search. These methods enable low-latency primitives for readout calibration, spectroscopy, pulse-amplitude calibration, coherence estimation, and benchmarking. We deploy this toolset to estimate T1 in 10 ms, optimize readout parameters in 100 ms, optimize pulse amplitudes in 1 ms, and perform Clifford randomized gate benchmarking in 107 ms on a flux-tunable superconducting transmon qubit. Running a closed-loop on-FPGA recalibration protocol continuously for 6 hours enables more than 74,000 consecutive recalibrations and yields gate errors that consistently retain better performance than the baseline initial calibration. Correlation analysis shows that recalibration suppresses coupling of gate error to control-parameter drift while preserving a coherence-linked performance. Finally, we quantify uncertainty versus time-to-decision under our sparse sampling approaches and identify optimal parameter regimes for efficient estimation of qubit and pulse parameters.