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arXiv:2011.05486 · IEEE Electron Device Letters

Variability and Fidelity Limits of Silicon Quantum Gates Due to Random Interface Charge Traps

Tong Wu, Jing Guo

Published Jan 1, 2020• 8 citations
arXivHTMLPDF

Abstract

Silicon offers an attractive material platform for hardware realization of quantum computing. In this study, a microscopic stochastic simulation method is developed to model the effect of random interface charge traps in silicon metal-oxide-semiconductor (MOS) quantum gates. The statistical results show that by using a fast two-qubit gate in isotopically purified silicon, the two-qubit silicon-based quantum gates have the fidelity >98% with a probability of 75% for the state-of-the-art MOS interface quality. By using a composite gate pulse, the fidelity can be further improved to >99.5% with the 75% probability. The variations between the quantum gate devices, however, are largely due to the small number of traps per device. The results highlight the importance of variability consideration due to random charge traps and potential to improve fidelity in silicon-based quantum computing.

DOI
10.1109/led.2020.2997009

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Silicon offers an attractive material platform for hardware realization of quantum computing. In this study, a microscopic stochastic simulation method is developed to model the effect of random interface charge traps in silicon metal-oxide-semiconductor (MOS) quantum gates. The statistical results show that by using a fast two-qubit gate in isotopically purified silicon, the two-qubit silicon-based quantum gates have the fidelity >98% with a probability of 75% for the state-of-the-art MOS interface quality. By using a composite gate pulse, the fidelity can be further improved to >99.5% with the 75% probability. The variations between the quantum gate devices, however, are largely due to the small number of traps per device. The results highlight the importance of variability consideration due to random charge traps and potential to improve fidelity in silicon-based quantum computing.
Silicon spin qubits are promising for large-scale quantum-computer integration because they can fully leverage the well-developed semiconductor infrastructure. However, the low fidelity of two-qubit entanglement gates remains a key barrier to large-scale integrations. Recent simulations of silicon spin-qubit two-qubit gates have been performed on silicon-on-insulator (SOI) platforms, while nanosheet-based charge-qubit work has been limited to single-qubit operation using a two-dimensional Schrödinger approximation. In this work, we study silicon spin-qubit double quantum dots built on nanosheet technology using the Quantum Technology Computer-Aided Design (QTCAD) simulation suite to run three-dimensional Poisson and Schroedinger solvers, followed by a many-body solver to extract exchange interactions. We evaluate the exchange energy sensitivity to process and bias variations and then use QuTiP to solve the master equation for a two-qubit gate. The results show that millivolt-level bias variations at the plunger and middle barrier gates can reduce the gate fidelity below 99%, a common threshold target for many fault-tolerant quantum-computing algorithms. Gate-referred 1/f charge-noise effects are also analyzed through the resulting coherence time.
The spin of an electron confined in semiconductor quantum dots is currently a promising candidate for quantum bit (qubit) implementations. Taking advantage of the existing CMOS integration technologies, such devices can offer a platform for large scale quantum computation. However, a quantum mechanical framework bridging a device's physical design and operational parameters to the qubit's energy space is lacking. Furthermore, the spin to charge coupling introduced by intrinsic or induced spin-orbit interaction (SOI) exposes the qubits to charge noise compromising their coherence properties and inducing quantum gate errors. We present here a comodeling framework for double quantum dot (DQD) devices and their charge noise environments. We use a combination of an electrostatic potential solver, full configuration interaction quantum mechanical methods, and two-level-fluctuator models to study the quantum gate performance in realistic device designs and operation conditions. We utilize the developed models together alongside the single electron solutions of the quantum dots to simulate one- and two-qubit gates in the presence of charge noise. We find an inverse correlation between quantum gate errors and quantum dot confinement frequencies. We calculate X-gate fidelities >97>97%>97 in the simulated Si-MOS devices at a typical TLF density of ${10}^{11}\phantom{\rule{4pt}{0ex}}{\mathrm{cm}}^{\ensuremath{-}2}$. We also find that exchange driven two-qubit SWAP gates show higher sensitivity to charge noise with fidelities down to 9191%91 in the presence of the same density of TLFs. We further investigate the one- and two-qubit gate fidelities at different TLF densities. We find that given the small size of the quantum dots, sensitivity of a quantum gate to the distance between the noise sources and the quantum dot creates a strong variability in the quantum gate fidelities, which can compromise the device yields in scaled qubit technologies.
We show that nonexponential fidelity decays in randomized benchmarking experiments on quantum-dot qubits are consistent with numerical simulations that incorporate low-frequency noise and correspond to a control fidelity that varies slowly with time. By expanding standard randomized benchmarking analysis to this experimental regime, we find that such nonexponential decays are better modeled by multiple exponential decay rates, leading to an instantaneous control fidelity for isotopically purified silicon metal-oxide-semiconductor quantum-dot qubits which is 98.9% when the low-frequency noise causes large detuning but can be as high as 99.9% when the qubit is driven on resonance and system calibrations are favorable. These advances in qubit characterization and validation methods underpin the considerable prospects for silicon as a qubit platform for fault-tolerant quantum computation.
Abstract Quantum computers offer a route to outperform classical methods in tasks such as molecular simulation, motivating hybrid algorithms like the variational quantum eigensolver (VQE) for near-term devices. Silicon spin qubits are a promising platform for scalable quantum computation, but their performance is limited by hardware imperfections—most notably charge-noise–induced potential fluctuations and static miscalibration of gate-electrode voltages—which degrade quantum gate fidelities and, ultimately, algorithmic accuracy. Here we develop a hardware–algorithm co-simulation framework for silicon quantum-dot processors that links 3D electrostatics to effective g -factors and exchange couplings, and propagates voltage-level noise through realistic control pulses. Using VQE for H 2 ground-state energy estimation as a circuit-level testbed, we study both static scaling/offset errors on the gate-electrode voltages and stochastic fluctuations modeled as random-telegraph noise with tunable amplitudes and switching times. At the gate level, we show that exchange-based two-qubit gates are roughly an order of magnitude more sensitive to these types of noise than ESR-driven single-qubit rotations. Quantum process tomography and Kraus-operator analysis further distinguish coherent and incoherent contributions and quantify the fraction of error that is, in principle, correctable by a compensating unitary. Embedding these noise models into the VQE circuit, we identify regimes of miscalibration strength and noise switching time compatible with chemically accurate energy estimates, and discuss how statistical post-processing based on the full distribution of noisy energy estimates could further improve accuracy.
Quantum computers offer a route to outperform classical methods in tasks such as molecular simulation, motivating hybrid algorithms like the Variational Quantum Eigensolver (VQE) for near-term devices. Silicon spin qubits are a promising platform for scalable quantum computation, but their performance is limited by hardware imperfections -- most notably charge-noise-induced potential fluctuations and static miscalibration of gate-electrode voltages -- which degrade quantum gate fidelities and, ultimately, algorithmic accuracy. Here we develop a hardware-algorithm co-simulation framework for silicon quantum-dot processors that links 3D electrostatics to effective ggg-factors and exchange couplings, and propagates voltage-level noise through realistic control pulses. Using VQE for H2\mathrm{H}_2H2​ ground-state energy estimation as a circuit-level testbed, we study both static scaling/offset errors on the gate-electrode voltages and stochastic fluctuations modeled as random-telegraph noise with tunable amplitudes and switching times. At the gate level, we show that exchange-based two-qubit gates are roughly an order of magnitude more sensitive to these types of noise than ESR-driven single-qubit rotations. Quantum process tomography and Kraus-operator analysis further distinguish coherent and incoherent contributions and quantify the fraction of error that is, in principle, correctable by a compensating unitary. Embedding these noise models into the VQE circuit, we identify regimes of miscalibration strength and noise switching time compatible with chemically accurate energy estimates, and discuss how statistical post-processing based on the full distribution of noisy energy estimates could further improve accuracy.
Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a quantum algorithm are examined. The results indicate the attractive potential to achieve high speed and fidelity silicon quantum gates with a low operation voltage. To scale up, reducing the device variability and mitigating the variability effect are identified to be indispensable for reliable implementing a quantum computing algorithm with the silicon quantum gates based on the detuning mechanism. A scheme to use the control electronics for mitigating the variability of quantum gates is proposed.