Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, we develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
<!--HTML-->Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this talk, we present a method to analyze the dimensional expressivity of parametric quantum circuits. This technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
The design of parametric quantum circuits (PQCs) for efficient use in variational quantum simulations (VQS) is subject to two competing factors. On one hand, the set of states that can be generated by the PQC has to be large enough to contain the solution state. Otherwise, one may at best find the best approximation of the solution restricted to the states generated by the chosen PQC. On the other hand, the PQC should contain as few parametric quantum gates as possible to minimize noise from the quantum device. Thus, when designing a PQC one needs to ensure that there are no redundant parameters. The dimensional expressivity analysis discussed in these proceedings is a means of addressing these counteracting effects. Its main objective is to identify independent and redundant parameters in the PQC. Using this information, superfluous parameters can be removed and the dimension of the space of states that are generated by the PQC can be computed. Knowing the dimension of the physical state space then allows us to deduce whether or not the PQC can reach all physical states. Furthermore, the dimensional expressivity analysis can be implemented efficiently using a hybrid quantum-classical algorithm. This implementation has relatively small overhead costs both for the classical and quantum part of the algorithm and could therefore be used in the future for on-the-fly circuit construction. This would allow for optimized circuits to be used in every loop of a VQS rather than the same PQC for the entire VQS. These proceedings review and extend work in [1, 2].
Variational quantum algorithms (VQAs) rely on parameterized quantum circuits (PQCs), whose performance is governed by expressibility and trainability. Existing studies typically evaluate these properties at the logical circuit level, implicitly assuming that designed PQCs remain unchanged during hardware execution. In practice, however, hardware-aware transpilation modifies circuit structure through qubit mapping, routing, and basis decomposition, potentially altering PQC behavior. In this paper, we perform a systematic hardware-aware analysis of expressibility and trainability by comparing logical and transpiled PQCs across multiple ansatz families, qubit counts, and circuit depths. Expressibility is measured using fidelity-based KL divergence, while trainability is quantified through gradient variance. Our results show that transpilation acts as an implicit architectural perturbation, producing strongly ansatz-dependent effects. Expressibility deviations exceed upto 125% in some cases, while trainability variations reach up to 25%. Structured ansatzes are generally more robust, whereas highly entangled architectures are more sensitive to transpilation-induced transformations. We further show that transpilation can alter the commonly assumed expressibility-trainability trade-off, demonstrating that logical-level analyses may not reliably predict hardware-level behavior. These findings highlight the importance of hardware-aware evaluation for accurate characterization of VQAs.
In Variational Quantum Simulations, the construction of a suitable parametric quantum circuit is subject to two counteracting effects. The number of parameters should be small for the device noise to be manageable, but also large enough for the circuit to be able to represent the solution. Dimensional expressivity analysis can optimize a candidate circuit considering both aspects. In this article, we will first discuss an inductive construction for such candidate circuits. Furthermore, it is sometimes necessary to choose a circuit with fewer parameters than necessary to represent all relevant states. To characterize such circuits, we estimate the best-approximation error using Voronoi diagrams. Moreover, we discuss a hybrid quantum-classical algorithm to estimate the worst-case best-approximation error, its complexity, and its scaling in state space dimensionality. This allows us to identify some obstacles for variational quantum simulations with local optimizers and underparametrized circuits, and we discuss possible remedies.
Abstract Parameterized quantum circuits (PQCs) play an essential role in the performance of many variational quantum algorithms. One challenge in implementing such algorithms is choosing an effective circuit that well represents the solution space while maintaining a low circuit depth and parameter count. To characterize and identify expressible, yet compact, circuits, several descriptors are proposed, including expressibility and entangling capability, that are statistically estimated from classical simulations. These descriptors are computed for different circuit structures, varying the qubit connectivity and selection of gates. From these simulations, circuit fragments that perform well with respect to the descriptors are identified. In particular, a substantial improvement in performance of two‐qubit gates in a ring or all‐to‐all connected arrangement, compared to that of those on a line, is observed. Furthermore, improvement in both descriptors is achieved by sequences of controlled X‐rotation gates compared to sequences of controlled Z‐rotation gates. In addition, it is investigated how expressibility “saturates” with increased circuit depth, finding that the rate and saturated value appear to be distinguishing features of a PQC. While the correlation between each descriptor and algorithm performance remains to be investigated, methods and results from this study can be useful for algorithm development and design of experiments.