As superconducting qubits continue to advance technologically, the realization of quantum algorithms from theoretical abstraction to physical implementation requires knowledge of both quantum circuit construction as well as hardware limitations. In this study we present results from experiments run on IBM's 20-qubit `Poughkeepsie' architecture, with the goal of demonstrating various qubit qualities and challenges that arise in designing quantum algorithms. These include experimentally measuring $T_1$ and $T_2$ coherence times, gate fidelities, sequential CNOT gates, techniques for handling ancilla qubits, and finally CCNOT and QFT $^{\dagger}$ circuits implemented on several different qubit geometries. Our results demonstrate various techniques for improving quantum circuits which must compensate for limited connectivity, either through the use of SWAP gates or additional ancilla qubits.As superconducting qubits continue to advance technologically, the realization of quantum algorithms from theoretical abstraction to physical implementation requires knowledge of both quantum circuit construction as well as hardware limitations. In this study we present results from experiments run on IBM's 20-qubit `Poughkeepsie' architecture, with the goal of demonstrating various qubit qualities and challenges that arise in designing quantum algorithms. These include experimentally measuring $T_1$ and $T_2$ coherence times, gate fidelities, sequential CNOT gates, techniques for handling ancilla qubits, and finally CCNOT and QFT$^{\dagger}$ circuits implemented on several different qubit geometries. Our results demonstrate various techniques for improving quantum circuits which must compensate for limited connectivity, either through the use of SWAP gates or additional ancilla qubits.

Mar 2, 20202 citations

Improving and benchmarking NISQ qubit routers

Vicente Pina-Canelles, Adrian Auer, Inés de Vega

Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to $84\%$ higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to $84\%$ higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.

arXiv:2502.03908Feb 6, 20250 citations

Early IBM quantum computers: architectural analysis and performance benchmarks

M. AbuGhanem

Abstract The emergence of noisy intermediate-scale quantum processors marked a pivotal stage in quantum computing, enabling the first demonstrations of quantum computational advantage despite limitations in qubit count, connectivity, and gate fidelity. Among the earliest and most accessible NISQ platforms were the IBM Quantum $^\texttt {TM}$ TM computers, which provided an open testbed for algorithm development, benchmarking, and error mitigation. Crucially, many of these pioneering quantum computers have since been retired, rendering their performance records fragmented and at risk of permanent loss. This work presents a comprehensive benchmarking study of these early IBM quantum computers, documenting their architectural layouts, qubit connectivity, native gate sets, coherence properties, effective Hamiltonians, control mechanisms, error rates, and operational performance. We reconstruct the operational profiles of these quantum computers and highlight the trends, trade-offs, and limitations that characterized superconducting quantum hardware in the NISQ era. This study establishes a historical baseline for assessing progress in quantum hardware development, offering essential guidance on error scaling, coherence limitations, and architectural trade-offs for designing next-generation quantum hardware. These insights directly inform superconducting quantum architecture design, compilation strategies, and error-resilient algorithms on the path toward fault-tolerant quantum computation.Abstract The emergence of noisy intermediate-scale quantum processors marked a pivotal stage in quantum computing, enabling the first demonstrations of quantum computational advantage despite limitations in qubit count, connectivity, and gate fidelity. Among the earliest and most accessible NISQ platforms were the IBM Quantum $$^\texttt {TM}$$ TM computers, which provided an open testbed for algorithm development, benchmarking, and error mitigation. Crucially, many of these pioneering quantum computers have since been retired, rendering their performance records fragmented and at risk of permanent loss. This work presents a comprehensive benchmarking study of these early IBM quantum computers, documenting their architectural layouts, qubit connectivity, native gate sets, coherence properties, effective Hamiltonians, control mechanisms, error rates, and operational performance. We reconstruct the operational profiles of these quantum computers and highlight the trends, trade-offs, and limitations that characterized superconducting quantum hardware in the NISQ era. This study establishes a historical baseline for assessing progress in quantum hardware development, offering essential guidance on error scaling, coherence limitations, and architectural trade-offs for designing next-generation quantum hardware. These insights directly inform superconducting quantum architecture design, compilation strategies, and error-resilient algorithms on the path toward fault-tolerant quantum computation.

The Journal of SupercomputingMay 18, 20261 citation

Experimental comparison of two quantum computing architectures

Norbert M. Linke, Dmitri A Maslov, Martin Roetteler +5 more

We run a selection of algorithms on two state-of-the-art 5-qubit quantum computers that are based on different technology platforms. One is a publicly accessible superconducting transmon device (www. RESEARCH: ibm.com/ibm-q) with limited connectivity, and the other is a fully connected trapped-ion system. Even though the two systems have different native quantum interactions, both can be programed in a way that is blind to the underlying hardware, thus allowing a comparison of identical quantum algorithms between different physical systems. We show that quantum algorithms and circuits that use more connectivity clearly benefit from a better-connected system of qubits. Although the quantum systems here are not yet large enough to eclipse classical computers, this experiment exposes critical factors of scaling quantum computers, such as qubit connectivity and gate expressivity. In addition, the results suggest that codesigning particular quantum applications with the hardware itself will be paramount in successfully using quantum computers in the future.We run a selection of algorithms on two state-of-the-art 5-qubit quantum computers that are based on different technology platforms. One is a publicly accessible superconducting transmon device (www. RESEARCH: ibm.com/ibm-q) with limited connectivity, and the other is a fully connected trapped-ion system. Even though the two systems have different native quantum interactions, both can be programed in a way that is blind to the underlying hardware, thus allowing a comparison of identical quantum algorithms between different physical systems. We show that quantum algorithms and circuits that use more connectivity clearly benefit from a better-connected system of qubits. Although the quantum systems here are not yet large enough to eclipse classical computers, this experiment exposes critical factors of scaling quantum computers, such as qubit connectivity and gate expressivity. In addition, the results suggest that codesigning particular quantum applications with the hardware itself will be paramount in successfully using quantum computers in the future.

arXiv:1702.01852Proceedings of the National Academy of SciencesMar 21, 2017504 citations

A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

Siyuan Niu, Adrien Suau, Gabriel Staffelbach +1 more

Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.

arXiv:2010.03397IEEE Transactions on Quantum EngineeringJan 1, 2020103 citations

Superconducting Qubits: Current State of Play

Morten Kjærgaard, Mollie E. Schwartz, Jochen Braumüller +4 more

Superconducting qubits are leading candidates in the race to build a quantum computer capable of realizing computations beyond the reach of modern supercomputers. The superconducting qubit modality has been used to demonstrate prototype algorithms in the noisy intermediate-scale quantum (NISQ) technology era, in which non-error-corrected qubits are used to implement quantum simulations and quantum algorithms. With the recent demonstrations of multiple high-fidelity, two-qubit gates as well as operations on logical qubits in extensible superconducting qubit systems, this modality also holds promise for the longer-term goal of building larger-scale error-corrected quantum computers. In this brief review, we discuss several of the recent experimental advances in qubit hardware, gate implementations, readout capabilities, early NISQ algorithm implementations, and quantum error correction using superconducting qubits. Although continued work on many aspects of this technology is certainly necessary, the pace of both conceptual and technical progress in recent years has been impressive, and here we hope to convey the excitement stemming from this progress.Superconducting qubits are leading candidates in the race to build a quantum computer capable of realizing computations beyond the reach of modern supercomputers. The superconducting qubit modality has been used to demonstrate prototype algorithms in the noisy intermediate-scale quantum (NISQ) technology era, in which non-error-corrected qubits are used to implement quantum simulations and quantum algorithms. With the recent demonstrations of multiple high-fidelity, two-qubit gates as well as operations on logical qubits in extensible superconducting qubit systems, this modality also holds promise for the longer-term goal of building larger-scale error-corrected quantum computers. In this brief review, we discuss several of the recent experimental advances in qubit hardware, gate implementations, readout capabilities, early NISQ algorithm implementations, and quantum error correction using superconducting qubits. Although continued work on many aspects of this technology is certainly necessary, the pace of both conceptual and technical progress in recent years has been impressive, and here we hope to convey the excitement stemming from this progress.

arXiv:1905.13641Annual Review of Condensed Matter PhysicsDec 17, 20191,544 citations

T_1

and

T_2

coherence times, gate fidelities, sequential CNOT gates, techniques for handling ancilla qubits, and finally CCNOT and QFT

^{\dagger}

circuits implemented on several different qubit geometries. Our results demonstrate various techniques for improving quantum circuits which must compensate for limited connectivity, either through the use of SWAP gates or additional ancilla qubits.

84\%

higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.

^\texttt {TM}

TM computers, which provided an open testbed for algorithm development, benchmarking, and error mitigation. Crucially, many of these pioneering quantum computers have since been retired, rendering their performance records fragmented and at risk of permanent loss. This work presents a comprehensive benchmarking study of these early IBM quantum computers, documenting their architectural layouts, qubit connectivity, native gate sets, coherence properties, effective Hamiltonians, control mechanisms, error rates, and operational performance. We reconstruct the operational profiles of these quantum computers and highlight the trends, trade-offs, and limitations that characterized superconducting quantum hardware in the NISQ era. This study establishes a historical baseline for assessing progress in quantum hardware development, offering essential guidance on error scaling, coherence limitations, and architectural trade-offs for designing next-generation quantum hardware. These insights directly inform superconducting quantum architecture design, compilation strategies, and error-resilient algorithms on the path toward fault-tolerant quantum computation.