The development of quantum annealing machines (QAMs) based on superconducting qubits has progressed greatly in recent years and these machines are now widely used in both academia and commerce. On the other hand, QAMs based on semiconductor nanostructures such as quantum dots (QDs) appear to be still at the initial elementary research stage because of difficulty in controlling the interaction between qubits. In this paper, we review a QAM based on a semiconductor nanostructures such as floating gates (FGs) or QDs from the viewpoint of the integration of qubits. We theoretically propose the use of conventional high-density memories such as NAND flash memories for the QAM rather than the construction of a semiconductor qubit system from scratch. A large qubit system will be obtainable as a natural extension of the miniaturization of commercial-grade electronics, although further effort will likely be required to achieve high-quality qubits.
The development of quantum annealing machines (QAMs) based on superconducting qubits has progressed greatly in recent years and these machines are now widely used in both academia and commerce. On the other hand, QAMs based on semiconductor nanostructures such as quantum dots (QDs) appear to be still at the initial elementary research stage because of difficulty in controlling the interaction between qubits. In this paper, we review a QAM based on a semiconductor nanostructures such as floating gates (FGs) or QDs from the viewpoint of the integration of qubits. We theoretically propose the use of conventional high-density memories such as NAND flash memories for the QAM rather than the construction of a semiconductor qubit system from scratch. A large qubit system will be obtainable as a natural extension of the miniaturization of commercial-grade electronics, although further effort will likely be required to achieve high-quality qubits.
Quantum annealing machines based on superconducting qubits, which have the potential to solve optimization problems faster than digital computers, are of great interest not only to researchers but also to the general public. Here, we propose a quantum annealing machine based on a semiconductor floating gate (FG) array. We use the same device structure as that of the commercial FG NAND flash memory except for small differences such as thinner tunneling barrier. We theoretically derive an Ising Hamiltonian from the FG system in its single-electron region. Recent high-density NAND flash memories are subject to several problems that originate from their small FG cells. In order to store information reliably, the number of electrons in each FG cell should be sufficiently large. However, the number of electrons stored in each FG cell becomes smaller and can be countable. So we utilize the countable electron region to operate single-electron effects of FG cells. Second, in the conventional NAND flash memory, the high density of FG cells induces the problem of cell-to-cell interference through their mutual capacitive couplings. This interference problem is usually solved by various methods using a software of error-correcting codes. We derive the Ising interaction from this natural capacitive coupling. Considering the size of the cell, 10 nm, the operation temperature is expected to be approximately that of a liquid nitrogen. If a commercial 64 Gbit NAND flash memory is used, ideally we expect it to be possible to construct 2 megabytes (MB) entangled qubits by using the conventional fabrication processes in the same factory as is used for manufacture of NAND flash memory. A qubit system of highest density will be obtained as a natural extension of the miniaturization of commonly used memories in this society.
Quantum annealing machines based on superconducting qubits, which have the potential to solve optimization problems faster than digital computers, are of great interest not only to researchers but also to the general public. In this paper, we propose a quantum annealing machine based on a semiconductor floating gate (FG) array. The purpose of using the architecture of nand flash memories is to reuse a mature technology to create large arrays of silicon qubits. Current high-density nand flash memories use sufficiently small FG cells to make the number of electrons stored in each cell small and countable. The high packing density of these cells creates mutual capacitive couplings that can be used to generate cell-to-cell interactions. We explore these characteristics to derive an Ising Hamiltonian for the FG system in the single-electron regime. Considering the size of a cell (10 nm), the ideal operation temperature of a quantum annealer based on FG cells is estimated to be approximately that of liquid nitrogen. Assuming the parameters of a commercial 64 Gbit nand, we estimate that it is possible to create 2-megabyte (MB) qubit systems solely using conventional fabrication processes. Our proposal demonstrates that a large qubit system can be obtained as a natural extension of the miniaturization of commercial-grade electronics, although more effort will likely be required to achieve high-quality qubits.
Hybrid semiconductor-superconductor qubits have recently emerged as a promising alternative to traditional platforms, combining material advantages with device-level tunability. A defining feature is their gate-tunable Josephson coupling, enabling superconducting qubit architectures with full electric-field control and offering a path toward scalable, low-crosstalk quantum processors. This approach seeks to merge benefits of superconducting and semiconductor qubits, for instance by encoding quantum information in the spin of a quasiparticle occupying an Andreev bound state, thus combining long coherence times with fast, flexible control. Progress has accelerated through bottom-up engineering of Andreev states in coupled quantum dot arrays, leading to architectures such as minimal Kitaev chains hosting Majorana zero modes. In parallel, Hamiltonian-protected designs aim to enhance resilience against local noise and decoherence by exploiting superconducting phase dynamics and discrete charge or flux degrees of freedom. This article reviews recent theoretical and experimental advances in hybrid qubits, providing an overview of physical mechanisms, device implementations, and emerging architectures, with emphasis on their potential for (topologically) protected quantum information processing. While many designs remain at proof-of-concept stage, rapid progress suggests practical demonstrations may soon be achievable.
Semiconductors, a significant type of material in the information era, are becoming more and more powerful in the field of quantum information. In recent decades, semiconductor quantum computation was investigated thoroughly across the world and developed with a dramatically fast speed. The research varied from initialization, control and readout of qubits, to the architecture of fault-tolerant quantum computing. Here, we first introduce the basic ideas for quantum computing, and then discuss the developments of single- and two-qubit gate control in semiconductors. Up to now, the qubit initialization, control and readout can be realized with relatively high fidelity and a programmable two-qubit quantum processor has even been demonstrated. However, to further improve the qubit quality and scale it up, there are still some challenges to resolve such as the improvement of the readout method, material development and scalable designs. We discuss these issues and introduce the forefronts of progress. Finally, considering the positive trend of the research on semiconductor quantum devices and recent theoretical work on the applications of quantum computation, we anticipate that semiconductor quantum computation may develop fast and will have a huge impact on our lives in the near future.
Throughout this Ph.D., the quest to build a quantum computer has accelerated, driven by ever-improving fidelities of conventional qubits and the development of new technologies that promise topologically protected qubits with the potential for lifetimes that exceed those of comparable conventional qubits. As such, there has been an explosion of interest in the design of an architecture for a quantum computer. This design would have to include high-quality qubits at the bottom of the stack, be extensible, and allow the layout of many qubits with scalable methods for readout and control of the entire device. Furthermore, the whole experimental infrastructure must handle the requirements for parallel operation of many qubits in the system. Hence the crux of this thesis: to design an architecture for a semiconductor-based quantum computer that encompasses all the elements that would be required to build a large scale quantum machine, and investigate the individual these elements at each layer of this stack, from qubit to readout to control.