In the quest to reboot computing, quantum annealing (QA) is an interesting candidate for a new capability. While it has not demonstrated an advantage over classical computing on a real-world application, many important regions of the QA design space have yet to be explored. In IARPA's Quantum Enhanced Optimization (QEO) program, we have opened some new lines of inquiry to get to the heart of QA, and are designing testbed superconducting circuits and conducting key experiments. In this paper, we discuss recent experimental progress related to one of the key design dimensions: qubit coherence. Using MIT Lincoln Laboratory's qubit fabrication process and extending recent progress in flux qubits, we are implementing and measuring QA-capable flux qubits. Achieving high coherence in a QA context presents significant new engineering challenges. We report on techniques and preliminary measurement results addressing two of the challenges: crosstalk calibration and qubit readout. This groundwork enables exploration of other promising features and provides a path to understanding the physics and the viability of quantum annealing as a computing resource.
In the quest to reboot computing, quantum annealing (QA) is an interesting candidate for a new capability. While it has not demonstrated an advantage over classical computing on a real-world application, many important regions of the QA design space have yet to be explored. In IARPA's Quantum Enhanced Optimization (QEO) program, we have opened some new lines of inquiry to get to the heart of QA, and are designing testbed superconducting circuits and conducting key experiments. In this paper, we discuss recent experimental progress related to one of the key design dimensions: qubit coherence. Using MIT Lincoln Laboratory's qubit fabrication process and extending recent progress in flux qubits, we are implementing and measuring QA-capable flux qubits. Achieving high coherence in a QA context presents significant new engineering challenges. We report on techniques and preliminary measurement results addressing two of the challenges: crosstalk calibration and qubit readout. This groundwork enables exploration of other promising features and provides a path to understanding the physics and the viability of quantum annealing as a computing resource.
Quantum annealing is a method to solve optimization problems that leverages quantum tunneling in a coupled qubit system. We present a detailed study of the coherence of a tunable capacitively-shunted flux qubit, designed for coherent quantum annealing applications. We find that for high qubit frequencies, thermal noise in the bias line makes a significant contribution to the relaxation, arising from the design choice to experimentally explore both fast annealing and high-frequency control. The measured dephasing rate is primarily due to intrinsic low-frequency flux noise in the two qubit loops, with additional contribution from the low-frequency noise of control electronics used for fast annealing. Our results characterize decoherence in a realistic setup for quantum annealing and are relevant for ongoing efforts toward building superconducting quantum annealers with increased coherence. Quantum annealers hold promise of outperforming classical computers in solving hard optimization problems, but one main challenge is understanding the role of noise in quantum annealing. Here, the authors characterize the relevant noise sources in a tunable flux qubit, a building block for quantum annealers, and provide a benchmark for future work on highly-coherent quantum annealers.
Although quantum annealing has received considerable interest as a potential computing paradigm, it has not met the key criterion of improved scaling over classical methods. Qubit coherence is currently a major limitation. Starting from a detailed theoretical understanding of the system, the authors demonstrate tunably coupled flux qubits with a circuit geometry similar to those used in existing annealers, but with coherence times that are roughly two orders of magnitude longer. Their design concepts are not limited to superconducting qubits, and could be generalized to other types being considered for quantum annealing.
Designing a qubit architecture is one of the most critical challenges in achieving scalable and fault-tolerant quantum computing as the performance of a quantum computer is heavily dependent on the coherence times, connectivity and low noise environments. Superconducting qubits have emerged as a frontrunner among many competing technologies, primarily because of their speed of operations, relatively well-developed and offer a promising path toward scalability. Here, we address the challenges of optimizing superconducting qubit hardware through the development of a comprehensive theoretical framework that spans the entire process - from design to the calibration of hardware through quantum gate execution. We develop this framework in four key steps: circuit design, electromagnetic analysis, spectral analysis, and pulse sequencing with calibration. We first refine the qubit's core components - such as capacitance, Josephson junctions, and resonators - to set the foundation for strong performance. The electromagnetic analysis, using the Lumped Oscillator model, allows us to map out the capacitance matrix, ensuring that we minimize spectral dispersion while maximizing coherence times. Following this, we conduct spectral analysis to fine-tune the qubit's frequency spectrum and coherence properties, ensuring that the qubit parameters are optimized. Finally, we focus on pulse sequencing, including pulse-width optimization, DRAG optimization, and randomized benchmarking, to achieve high gate fidelity. We applied this framework to both Transmon and Fluxonium qubits, obtaining results that closely match those found in experimental studies. This work provides a detailed and practical approach to the design, optimization, and calibration of superconducting qubits, contributing to the broader effort to develop scalable quantum computing technologies.
Critical decision-making issues in science, engineering, and industry are based on combinatorial optimization; however, its application is inherently limited by the NP-hard nature of the problem. A specialized paradigm of analogue quantum computing, quantum annealing (QA), has been proposed to solve these problems by encoding optimization problems into physical energy landscapes and solving them by quantum tunnelling systematically through exploration of solution space. This is a critical review that summarizes the current applications of quantum annealing to combinatorial optimization and includes a theoretical background, hardware designs, algorithm implementation strategies, encoding and embedding schemes, protocols to benchmark quantum annealing, areas of implementation, and links with the quantum algorithms implementation with gate-based hardware and classical solvers. We develop a unified framework, relating adiabatic quantum dynamics, Ising and QUBO models, stoquastic and non-stoquastic Hamiltonians, and diabatic transitions to modern flux-qubit annealers (Chimera, Pegasus, Zephyr topologies), and emergent architectures (Lechner-Hauke-Zoller systems, Rydberg atom platforms), and hybrids of quantum and classical computation. Through our analysis, we find that overhead in embedding and encoding is the largest determinant of the scalability and performance (this is not just the number of qubits). Minor embeddings also usually have a physical qubit count per logical variable of between 5 and 12 qubits, which limits effective problem capacity by 80-92% and, due to chain-breaking errors, compromises the quality of solutions.
Combinatorial optimization is a foundation of numerous scientific, industrial, and social decision-making questions, but its usefulness is mostly restricted by the exponential complexity of the problem of classical computability. The quantum annealing (QA) has become one of the leading analogue quantum systems to address such problems, whereby optimization problems are converted into physical energy structures and quantum fluctuations are utilized to perform systematic exploration. It provides a critical, synthesized, and comprehensive review of quantum annealing as applied to combinatorial optimization, including the theoretical basis, hardware designs, algorithm methods, issues of embedding and encoding, benchmarking procedures, applications, and integration with quantum algorithms based on gates and solvers on a classical computer. We build a comprehensive taxonomy between adiabatic dynamics, Ising and QUBO models, stoquastic and non-stoquastic Hamiltonians, and diabatic transitions to state-of-the-art flux-qubit annealers, new architectures, and hybrid quantum classical pipelines. We show that the overhead of embedding and encoding and the benchmarking approach taken are the most significant factors in determining scalability and performance, but not the raw number of qubits. Transportation, energy systems, robotics, finance, pharmacological discovery, and machine learning are just some examples of the domain-specific case studies that use QA with minimal empirical utility as a hybrid refinement engine and not an independent solver. Moreover, we introduce a stringent evaluation of the existing benchmarking culture, clarify the causal links between QA and QAOA as well as between VQE and structural predicaments, and reveal the institutional roots of the existing restrictions. We conclude by identifying a research roadmap in the future, focusing on the annealing hardness characterization, Stoquastic control manipulation, embedding rules automation, architecture design, and development of principled quantum advantage. It creates a benchmark reference to those in the field and research and deployment of scalable, reliable, and application-relevant quantum optimization
We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).