Privacy amplification is an indispensable step in postprocessing of continuous-variable quantum key distribution (CV-QKD), which is used to distill unconditional secure keys from identical corrected keys between two distant legal parties. The processing speed of privacy amplification has a significant effect on the secret key rate of a CV-QKD system. We report the high-speed parallel implementation of the length-compatible privacy amplification algorithm based on a graphic processing unit. The length-compatible algorithm is used to satisfy the security requirements of privacy amplification at different transmission distances when considering finite-size effect. We achieve the speed of privacy amplification over 1 Gb/s at arbitrary input length and the speed is one to two orders of magnitude faster than previous demonstrations, which supports the high-speed real-time CV-QKD system and ensures the security of privacy amplification.
Privacy amplification is an indispensable step in postprocessing of continuous-variable quantum key distribution (CV-QKD), which is used to distill unconditional secure keys from identical corrected keys between two distant legal parties. The processing speed of privacy amplification has a significant effect on the secret key rate of a CV-QKD system. We report the high-speed parallel implementation of the length-compatible privacy amplification algorithm based on a graphic processing unit. The length-compatible algorithm is used to satisfy the security requirements of privacy amplification at different transmission distances when considering finite-size effect. We achieve the speed of privacy amplification over 1 Gb/s at arbitrary input length and the speed is one to two orders of magnitude faster than previous demonstrations, which supports the high-speed real-time CV-QKD system and ensures the security of privacy amplification.
Privacy amplification (PA) is an essential process for high-speed and real-time implementation of a continuous-variable quantum key distribution (CV-QKD) system. This work focuses on the improvement of the performance of PA, and we realize PA with Toeplitz matrix and accelerate it using fast Fourier transform (FFT) on graphic processing unit (GPU). Based on the architectural feature of FFT, we adjust its form of input length and obtained an average speed of PA about 2Gbps with input length ranges from 1Mbits to 128Mbits, which is length-adaptable to satisfy various requirements of CV-QKD systems at different transmission distances. Furthermore, we test this work with different compress ratios of PA, which can also achieve a high implementation speed around 2Gbps. With the method used in this paper, the requirements of PA for the high-speed and real-time CV-QKD system can be entirely satisfied.
For a high-speed and secure continuous-variable quantum key distribution (CV-QKD) system, privacy amplification (PA) plays an important role. To reduce the finite size effect, the input length of PA should be at least on the order of 10^8, 10^9, 10^10 when the transmission distance is about 50km, 80km, 100km, respectively. This leads to high computation complexity and large storage demand of the data, which is unfriendly to field programmable gate array (FPGA) implementation for its limited resource. In addition, the limited IO speed of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) restricts the implementation performance of PA. In this paper, we propose an effective way to access data based on DDR to improve the performance of PA. As a result, the reading time from DDR can be reduced, and it can eliminate the effect of the limited IO speed of DDR, so that PA can perform with multiple code-words. This can make full use of the resource of FPGA and increase the execution speed of PA. Besides, combining with the proposed method, an easier algorithm is used to decrease the complexity of calculations. Based on these methods, we realize PA with Toeplitz matrix based on FPGA and the experimental throughput is about 288Mbps when the input length is about 100Mbits.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
Post-processing is indispensable in quantum key distribution (QKD), which is aimed at sharing secret keys between two distant parties. It mainly consists of key reconciliation and privacy amplification, which is used for sharing the same keys and for distilling unconditional secret keys. In this paper, we focus on speeding up the privacy amplification process by choosing a simple multiplicative universal class of hash functions. By constructing an optimal multiplication algorithm based on four basic multiplication algorithms, we give a fast software implementation of length-adaptive privacy amplification. "Length-adaptive" indicates that the implementation of privacy amplification automatically adapts to different lengths of input blocks. When the lengths of the input blocks are 1 Mbit and 10 Mbit, the speed of privacy amplification can be as fast as 14.86 Mbps and 10.88 Mbps, respectively. Thus, it is practical for GHz or even higher repetition frequency QKD systems.
Privacy amplification is an indispensable procedure to share secure secret key between legitimate parties in quantum key distribution (QKD) because a portion of bits are still leaked to eavesdropper Eve after the secret reconciliation. Here, we propose a novel privacy amplification scheme with an optimal hash function. In particular, by utilizing the linear feedback shift register (LFSR) technique, we optimize and simplify the construction of the Toeplitz matrix. In this way, the LFSR-based Toeplitz matrix is used to execute the privacy amplification algorithm. The hardware storage resources can then be drastically saved, and the time consuming will be only about half of that without using the LFSR-based Toeplitz matrix. This work breaks the bottleneck of privacy amplification in high-speed continuous-variable QKD (CVQKD), and thus contributes to the real-time performance of the whole CVQKD system.
Abstract Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD), ensuring security against eavesdropping by eliminating information leakage. For Discrete-Variable QKD (DV-QKD) protocols, a large input block size exceeding 108 bits is preferred to achieve the secure key rate approaching the asymptotic limit. However, in state-of-the-art quantum key distribution systems operating at multi-GHz pulse rates, PA becomes a critical bottleneck due to the conflicting requirements of large input block sizes and high throughput. To address this challenge, we propose a novel PA algorithm utilizing a newly constructed universal hash family DM3H and prove its cryptographic security rigorously. Based on the PA algorithm, we design and implement an efficient PA scheme which is capable of processing input block sizes up to 10 10 bits while achieving high throughput performance. For an input block size of 1010 bits, the implementation on the i9-14900 platform demonstrates a throughput of 112 Mbps with a retention ratio of 0.33. This breakthrough significantly enhances the secure key rate and maximum transmission distance of DV-QKD systems.