Superconducting Caps for Quantum Integrated Circuits
William B. O’Brien, Mehrnoosh Vahidpour, Jon Tyler Whyland, Joel Angeles, Jayss Marshall, Diego Scarabelli, Genya Crossman, Kamal Yadav, Yuvraj Mohan, Cat-Vu H. Bui, Vijay Rawat, Russ Renzas, Nagesh Vodrahalli, Andrew J. Bestwick, Chad T. Rigetti
We report on the fabrication and metrology of superconducting caps for qubit circuits. As part of a 3D quantum integrated circuit architecture, a cap chip forms the upper half of an enclosure that provides isolation, increases vacuum participation ratio, and improves performance of individual resonant elements. Here, we demonstrate that such caps can be reliably fabricated, placed on a circuit chip, and form superconducting connections to the circuit.
We report on the fabrication and metrology of superconducting caps for qubit circuits. As part of a 3D quantum integrated circuit architecture, a cap chip forms the upper half of an enclosure that provides isolation, increases vacuum participation ratio, and improves performance of individual resonant elements. Here, we demonstrate that such caps can be reliably fabricated, placed on a circuit chip, and form superconducting connections to the circuit.
Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo> 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.
Superconducting enclosures will be key components of scalable quantum computing devices based on circuit quantum electrodynamics. Within a densely integrated device, they can protect qubits from noise and serve as quantum memory units. Whether constructed by machining bulk pieces of metal or microfabricating wafers, 3D enclosures are typically assembled from two or more parts. The resulting seams potentially dissipate crossing currents and limit performance. In this letter, we present measured quality factors of superconducting cavity resonators of several materials, dimensions, and seam locations. We observe that superconducting indium can be a low-loss RF conductor and form low-loss seams. Leveraging this, we create a superconducting micromachined resonator with indium that has a quality factor of two million, despite a greatly reduced mode volume. Inter-layer coupling to this type of resonator is achieved by an aperture located under a planar transmission line. The described techniques demonstrate a proof-of-principle for multilayer microwave integrated quantum circuits for scalable quantum computing.
This work presents a comprehensive analytical and simulation-based study of superconducting quantum chip architectures, spanning both 2D planar and 3D-integrated designs. We first design and simulate a planar quantum chip layout using Qiskit Metal, which is imported into Ansys HFSS (High Frequency Structure Simulator) to construct a 3D model and perform electromagnetic simulations. A detailed analysis using Driven Modal, Eigenmode, Magnetostatic, and Q3D Capacitance Extraction solvers ensures our simulations accurately reflect physical behavior. The results are validated against analytical models from microwave engineering. pyEPR (Python Energy Participation Ratio) is used to extract key quantum metrics, including eigenfrequencies, quality factors, decoherence times, anharmonicity, cross-Kerr interactions, and participation ratios. Building on this planar design, we extend our study to a 3D-integrated flip-chip architecture featuring two superconducting qubits fabricated on separate high-resistivity silicon substrates. Using HFSS and analytical modeling, we show that detuned qubits maintain stable eigenfrequencies, quality factors, decoherence times, anharmonicity, and cross-Kerr interactions over varying substrate separation values. However, the introduction of dielectric loss tangents reduces quality factors which degrades coherence times and introduces an additional dephasing. These findings highlight the potential of 3D quantum integration, given minimal material imperfections.The planar and 3D designs together form a cohesive investigation into next-generation quantum hardware, with the 2D layout currently taped-out and under fabrication.
Superconducting quantum circuits (SQCs), composed of superconducting capacitors, inductances, Josephson junctions, and transmission lines, exhibit macroscopic quantum effects at ultra-low temperatures. Due to the extremely low dissipation of superconductors, an important application of SQCs is superconducting qubits with long coherence time. Quantum computing based on superconducting qubits is a leading physical realization method of quantum computing, which is theoretically capable of accelerating many computational problems including quantum simulation, database searching, and optimization. In the long run, to use the power of quantum computing to its full extent, universal quantum computers should be constructed with quantum error correction. In the short term, one of the most pressing targets of the superconducting quantum computing community is to demonstrate quantum advantage using noisy intermediate-scale quantum chips. Both goals rely on the increasing of the number of coupled qubits in a quantum circuit and the quality of these qubits, which dictate the breadth and the depth of a problem it can solve, respectively. The fabrication of SQCs has adopted a few manufacturing processes from conventional integrated circuits. Quantum chips containing multiple superconducting qubits can be made and packaged on a large scale. “Quantum supremacy” has been demonstrated on a quantum chip with fifty-three qubits fabricated using the flip-chip bonding technology. However, to demonstrate quantum advantage, the quality and quantity of qubits need to increase simultaneously. Dissipative channels emerge in circuit design, material preparation, chip fabrication, and working environment, limiting the lifetime of superconducting qubits. For quantum chips with tens to hundreds of qubits, the integration will also introduce extra processing steps which may degrade the qubits, and unwanted coupling to loss channels. Most of these channels are microscopically related to materials constructing the quantum chips, chip surfaces, and material interfaces. Thus, it is important to investigate the material growth and device fabrication of SQCs, and to understand the material related loss mechanisms. This review paper investigates the material related topics in superconducting quantum circuits pertinent to the quantum computing application from a comprehensive perspective. The history of SQCs is briefly mentioned, followed by the peculiar characteristics as an engineerable quantum system, and a roadmap to quantum advantage and universal quantum computing in the next a few years. Technically, the superconducting quantum computer is compared to a Schrodinger’s cat, and can be boiled down into three parts, i.e., quantum chips, the environment, and the operating system, corresponding to the cat, the box, and the observer, respectively. The material related decoherence channels of the SQCs can be sorted into four categories; each will be discussed in details. To fabricate SQCs with minimal loss, the processing technologies are elaborated, including qubit design, material selection, surface treatments, film growth, and Josephson junction, etc. Though there are general guidelines that amorphous materials should be avoided and processing induced damage should be minimized, more is to be investigated due to the emerging of new materials and new fabrication methods. The last part presents the potential application of the superconducting quantum computer and its current state of play. SQC for quantum computing is a multi-discipline research topic, demanding joint efforts from different scientific and technical areas. Materials science and device processing will play important roles along the way to quantum practicality.