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arXiv:1704.08176 · IEEE International Superconductive Electronics Conference (ISEC)

Ring Oscillators for Clocking Reversible Superconducting Circuits and Fabrication Process Benchmarking

Vasili K. Semenov, Yuri A. Polyakov, Sergey K. Tolpygo

Published Jun 1, 2017• 2 citations
arXivHTMLPDF

Abstract

Existing concepts of reversible superconducting circuits as well as demonstrated adiabatic circuits require three-phase bias/clock signals generated by room temperature sources. A while ago, we suggested that a multi-phase bias/clock could be provided by a local Josephson junction-based generator. The generator looks like a long annular Josephson junction, only composed of discreet elements - junctions and inductors, and closed into a ring via a flux pump to inject any required number of vortices into the ring. A steady motion of the vortices forced by a uniformly distributed dc bias current applied to the ring is accompanied by a nearly harmonic ac currents flowing via the Josephson junctions (JJs) connected in series with small inductors. These ac currents serve as multi-phase bias/clock for nSQUID-based circuitry. To verify this concept and compare the dissipated energy with kBTln2 threshold, we developed a ring composed of 256 unshunted JJs with 20 μA target critical current, Ic. We investigated the behavior of the ring oscillator at each vortex count from 0 to 256. The measured critical current of the ring with vortices was about 0.1 μA per one JJ, which can be explained by unavoidable nonuniformity of the ring components and the influence of fluxes frozen near the ring. The corresponding energy dissipation, about 10kBT per passage of one vortex through one JJ, should be reduced further for prospective experiments with reversible circuits. However, obtained I-V characteristics could be of interest for scientists working with long Josephson junctions. Superiority of the fabrication process used in this work is demonstrated by the obtained about 200 times reduction of Icof the ring with vortices with respect to a single comprising JJ, much larger than in any previously described case.

DOI
10.1109/isec.2017.8314239

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Existing concepts of reversible superconducting circuits as well as demonstrated adiabatic circuits require three-phase bias/clock signals generated by room temperature sources. A while ago, we suggested that a multi-phase bias/clock could be provided by a local Josephson junction-based generator. The generator looks like a long annular Josephson junction, only composed of discreet elements - junctions and inductors, and closed into a ring via a flux pump to inject any required number of vortices into the ring. A steady motion of the vortices forced by a uniformly distributed dc bias current applied to the ring is accompanied by a nearly harmonic ac currents flowing via the Josephson junctions (JJs) connected in series with small inductors. These ac currents serve as multi-phase bias/clock for nSQUID-based circuitry. To verify this concept and compare the dissipated energy with kBTln2 threshold, we developed a ring composed of 256 unshunted JJs with 20 μA target critical current, Ic. We investigated the behavior of the ring oscillator at each vortex count from 0 to 256. The measured critical current of the ring with vortices was about 0.1 μA per one JJ, which can be explained by unavoidable nonuniformity of the ring components and the influence of fluxes frozen near the ring. The corresponding energy dissipation, about 10kBT per passage of one vortex through one JJ, should be reduced further for prospective experiments with reversible circuits. However, obtained I-V characteristics could be of interest for scientists working with long Josephson junctions. Superiority of the fabrication process used in this work is demonstrated by the obtained about 200 times reduction of Icof the ring with vortices with respect to a single comprising JJ, much larger than in any previously described case.
We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators of annular geometry. Being a topologically closed system and unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated a high quality factor. The novel design of an annular junction clock that allows easier interface with RSFQ circuitry has been realized. Magnetic fluxons are inserted into an annular LJJ by local injection of current into the control line of the junction. This technique resolves the long-standing problem of achieving superior stability of the fluxon state for application as a clock source. The linewidth of the phase-locked clock source is measured as low as 24 Hz relative to a reference oscillator at 40 GHz. The cycle-to-cycle jitter was measured to be 9 fs at a frequency of 36 GHz, or 0.04% of the clock period which is in good agreement with theoretical estimation.
On-chip, high-frequency clock sources are essential for the future development of superconductor digital circuits and systems. We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators that offer extremely low jitter. To meet the requirement for time-interleaved clock signals of complementary phase, two-phase 30 and 50 GHz clock sources using LJJ's have been developed with both linear and annular geometry. Unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated superior stability and higher quality factor (>10/sup 6/) than the linear LJJ oscillator. The LJJ oscillator with linear geometry is easier to interface with RSFQ circuitry since it has well-defined boundaries at either end, facilitating a two-phase clock source. On the other hand, multiple clock phases may be derived from an annular LJJ oscillator by connecting interface circuitry at various points around the circular junction, if the interface circuitry does not interfere with the fluxon(s) in the annular junction. Experimental results for two-phase RSFQ clock sources based on linear and annular LJJ oscillators are presented.
We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106cm-2junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 μA/μm2critical current density and 200 nm minimum linewidth of inductors.
We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.
One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the superconductor ADC technology matures toward more complex designs for higher dynamic range performance, the need for synchronous clocking of multiple comparators continues to grow. Since high-frequency external clock sources are expensive and make a significant contribution to the heat load of the system, a high-frequency and low-jitter on-chip clock source using long Josephson junction (LJJ) is considered the preferred long-term solution. Toward that end, we are working on improving an on-chip 110-GHz clock source based on an unshunted LJJ in annular geometry. Minimizing the additional jitter added by each fan-out of the clock signal is the effort's goal. For synchronous clocking of up to three comparators, we compare clock distribution using superconducting passive transmission lines and a new approach using novel active transmission lines. We also introduce a method of synchronizing LJJ clock source with an external stable oscillator by injection locking.