Surface codes represent a promising route towards universal fault-tolerant quantum computation, allowing for the protection of stored quantum states against many types of errors. This theoretical work shows that, in addition, a significantly enhanced versatility in quantum information processing is expected when qubits are encoded into the Majorana bound states in topological superconductor-semiconductor heterostructures. In view of recent experimental evidence for Majorana states in such heterostructures, a two-dimensional network of interacting Majorana states thus may feature key advantages towards the long-term goal of a functional quantum computer. The authors discuss how topologically protected logical qubits in this Majorana surface code architecture can be defined, initialized, manipulated, and read out. The physical ingredients needed to implement such operations are familiar from topologically trivial quantum devices. In particular, by employing quantum interference terms in conductance measurements, composite single-electron pumping protocols, and gate-tunable tunnel barriers, the full set of gates required for universal quantum computation can be implemented.
Surface codes represent a promising route towards universal fault-tolerant quantum computation, allowing for the protection of stored quantum states against many types of errors. This theoretical work shows that, in addition, a significantly enhanced versatility in quantum information processing is expected when qubits are encoded into the Majorana bound states in topological superconductor-semiconductor heterostructures. In view of recent experimental evidence for Majorana states in such heterostructures, a two-dimensional network of interacting Majorana states thus may feature key advantages towards the long-term goal of a functional quantum computer. The authors discuss how topologically protected logical qubits in this Majorana surface code architecture can be defined, initialized, manipulated, and read out. The physical ingredients needed to implement such operations are familiar from topologically trivial quantum devices. In particular, by employing quantum interference terms in conductance measurements, composite single-electron pumping protocols, and gate-tunable tunnel barriers, the full set of gates required for universal quantum computation can be implemented.
Surface codes have emerged as promising candidates for quantum information processing. Building on the previous idea to realize the physical qubits of such systems in terms of Majorana bound states supported by topological semiconductor nanowires, we show that the basic code operations, namely projective stabilizer measurements and qubit manipulations, can be implemented by conventional tunnel conductance probes and charge pumping via single-electron transistors, respectively. The simplicity of the access scheme suggests that a functional code might be in close experimental reach.
We propose a physical realization of a commuting Hamiltonian of interacting Majorana fermions realizing Z 2 topological order, using an array of Josephson-coupled topological superconductor islands. The required multi-body interaction Hamiltonian is naturally generated by a combination of charging energy induced quantum phase-slips on the superconducting islands and electron tunneling between islands. Our setup improves on a recent proposal for implementing a Majorana fermion surface code (Vijay et al 2015 Phys. Rev. X 5 041038 ), a 'hybrid' approach to fault-tolerant quantum computation that combines (1) the engineering of a stabilizer Hamiltonian with a topologically ordered ground state with (2) projective stabilizer measurements to implement error correction and a universal set of logical gates. Our hybrid strategy has advantages over the traditional surface code architecture in error suppression and single-step stabilizer measurements, and is widely applicable to implementing stabilizer codes for quantum computation.
We describe a concrete device roadmap toward a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits. Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits rather than directly on physical qubits; and a topological qubit array supporting lattice surgery demonstrations on two logical qubits. Devices that enable this path require a superconductor-semiconductor heterostructure that supports a topological phase, quantum dots and coupling between those quantum dots that can create the appropriate loops for interferometric measurements, and a microwave readout system that can perform fast, low-error single-shot measurements. We describe the key design components of these qubit devices, along with the associated protocols for demonstrations of single-qubit benchmarking, Clifford gate execution, quantum error detection, and quantum error correction, which differ greatly from those in more conventional qubits. Finally, we comment on implications and advantages of this architecture for utility-scale quantum computation.
Quantum computers are devices that can solve certain problems faster than ordinary, classical computers. The fundamental units of quantum information are qubits, superpositions of two states, a "zero" state and a "one" state. There are various approaches to construct such two-level systems, among others, using superconducting circuits, trapped ions or photons. A common feature of these physical systems is that their coherence times are relatively short compared to the length of useful computations. Superconducting qubits, for instance, are currently the most advanced solid-state qubits, but they decohere after around 100 microseconds, and any information stored in these qubits is lost. On the other hand, useful quantum computations may require quantum information to survive on time scales that are many orders of magnitude longer, as their runtimes can reach several hours or even days. Topological quantum computing is an approach to construct qubits that survive for the entire duration of such a long computation. Topological quantum computing comes in two flavors. The condensed matter approach is to build error-resilient qubits using exotic quasiparticles in topological materials, most prominently Majorana zero modes in topological superconductors. Even though no such qubit has been built to date, the hope is that their coherence times may be significantly longer than the coherence times of currently available solid-state qubits, but are still expected to be too short for large-scale quantum computing. The quantum information approach is to combine many error-prone qubits to build more robust logical qubits using topological error-correcting codes, e.g., surface codes. Even though the first approach is hardware-based and the second approach is software-based, they are deeply related. With Majorana-based qubits, the main logical operations are Majorana fermion parity measurements. By replacing Majorana-based qubits with surface-code patches and parity measurements with lattice-surgery operations, schemes for quantum computation with Majorana-based qubits or with surface codes can be identical. In this thesis, we explore how to construct a large-scale topological fault-tolerant quantum computer that can perform useful quantum computations. Here, topological refers to the nature of the quantum error-correcting code, while the underlying hardware may be based on non-topological qubits, but could also be composed of Majorana-based qubits. We provide a complete picture of such a large-scale device, breaking down large quantum computations into logical qubits and logical operations, describing how these logical operations are performed on the level of physical qubits and physical gates, and finally discussing how these physical qubits can be pieced together in a Majorana-based system using topological superconducting nanowires.
Majorana zero modes (MZMs) are promising candidates for topologically-protected quantum computing hardware, however their large-scale use will likely require quantum error correction. Majorana surface codes (MSCs) have been proposed to achieve this. However, many MSC properties remain unexplored. We present a unified framework for MSC "twist defects" – anyon-like objects encoding quantum information. We show that twist defects in MSCs can encode twice the amount of topologically protected information as in qubit-based codes or other MSC encoding schemes. This is due to twists encoding both logical qubits and "logical MZMs," with the latter enhancing the protection microscopic MZMs can offer. We explain how to perform universal computation with logical qubits and logical MZMs while potentially using far fewer resources than in other MSC schemes. All Clifford gates can be implemented on logical qubits by braiding twist defects. We introduce lattice-surgery-based techniques for computing with logical MZMs and logical qubits, achieving the effect of Clifford gates with zero time overhead. We also show that logical MZMs may result in improved spatial overheads for sufficiently low rates of quasi-particle poisoning. Finally, we introduce a novel MSC analogue of transversal gates that achieves encoded Clifford gates in small codes by braiding microscopic MZMs. MSC twist defects thus open new paths towards fault-tolerant quantum computation.
Quantum information protected by the topology of the storage medium is expected to exhibit long coherence times. Another feature is topologically protected gates generated through braiding of Majorana bound states (MBSs). However, braiding requires structures with branched topological segments which have inherent difficulties in the semiconductor–superconductor heterostructures now believed to host MBSs. In this paper, we construct quantum bits taking advantage of the topological protection and non-local properties of MBSs in a network of parallel wires, but without relying on braiding for quantum gates. The elementary unit is made from three topological wires, two wires coupled by a trivial superconductor and the third acting as an interference arm. Coulomb blockade of the combined wires spawns a fractionalized spin, non-locally addressable by quantum dots used for single-qubit readout, initialization, and manipulation. We describe how the same tools allow for measurement-based implementation of the Clifford gates, in total making the architecture universal. Proof-of-principle demonstration of topologically protected qubits using existing techniques is therefore within reach.