To build a quantum computer, one can simplify the design of multi-qubit elements (logic gates) by treating them as series of well known one- and two-qubit gates---at the price of a slower processor. What if there were a handy means for $d\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}t$ multi-qubit design? The authors show numerically that, under existing experimental constraints, their recently developed SuSSADE scheme can yield three-qubit gates for single-shot entangling operations with fidelity greater than 99.9%. This powerful approach brings us that much closer to a fault-tolerant solid-state quantum computer.
To build a quantum computer, one can simplify the design of multi-qubit elements (logic gates) by treating them as series of well known one- and two-qubit gates---at the price of a slower processor. What if there were a handy means for d\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}t multi-qubit design? The authors show numerically that, under existing experimental constraints, their recently developed SuSSADE scheme can yield three-qubit gates for single-shot entangling operations with fidelity greater than 99.9%. This powerful approach brings us that much closer to a fault-tolerant solid-state quantum computer.
Fault-tolerant quantum computing requires encoding the quantum information into logical qubits and performing the quantum information processing in a code-space. Quantum error correction codes, then, can be employed to diagnose and remove the possible errors in the quantum information, thereby avoiding the loss of information. Although a series of single- and two-qubit gates can be employed to construct a quantum error correcting circuit, however this decomposition approach is not practically desirable because it leads to circuits with long operation times. An alternative approach to designing a fast quantum circuit is to design quantum gates that act on a multi-qubit gate. Here I devise quantum control schemes to design high-fidelity single-shot multi-qubit (up to three) quantum gates. Quantum control task is to steer quantum dynamics towards closely realizing specific quantum operation by varying the external control parameters (external field) such that the resultant evolution closely approximates the desired evolution. A set of instructions that determines the control parameters, and hence the effectiveness of the control scheme, is called a policy. Machine learning algorithms can be employed to find successful policies for designing quantum gates. In particular, we employ supervised machine learning techniques to generate these successful policies. Finding successful policies is a feasibility problem for which optimization algorithms can be employed. Greedy algorithms are at the heart of machine learning techniques. They converge faster onto a successful policy and require less-computational resource than non-greedy algorithms. However, there is no guarantee that greedy algorithms succeed to a feasible solution when there exist constraints on i) gate operation time ii) computational resources, and iii) experimental resources. Our results show the failure of standard greedy machine learning algorithms and the superiority of non-greedy machine learning algorithms over greedy ones for designing quantum logic gates, when there exist constraints on the quantum system. We have also observed the failure of existing greedy and non-greedy techniques for designing high-fidelity three-qubit gates. Hence, we devised our machine learning technique called Subspace-Selective Self-adaptive Differential Evolution (SuSSADE). Each three-qubit gate designed by SuSSADE operates as fast as an entangling two-qubit gate under the same experimental constraints.
Quantum algorithms often benefit from the ability to execute multi-qubit (>2) gates. To date, such multi-qubit gates are typically decomposed into single- and two-qubit gates, particularly in superconducting qubit architectures. The ability to perform multi-qubit operations in a single step could vastly improve the fidelity and execution time of many algorithms. Here, we propose a single shot method for executing an i-Toffoli gate, a three-qubit gate with two control and one target qubit, using currently existing superconducting hardware. We show numerical evidence for a process fidelity over 99.5% and a gate time of 450 ns for superconducting qubits interacting via tunable couplers. Our method can straight forwardly be extended to implement gates with more than two control qubits at similar fidelities.
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Fault-tolerant quantum computing requires not only reliable logical qubit storage, but also the ability to perform high-fidelity logical operations between error-corrected qubits at scale. While much of the existing literature focuses on optimizing syndrome extraction for a single logical qubit, the co-design of physical architectures that support both robust error correction and efficient logical computation remains an open challenge. In this work, we propose a multi-qubit spin-qubit shuttling bus architecture that addresses both requirements simultaneously. The architecture optimizes the physical qubit layout for syndrome extraction and supports transversal two-qubit logical gates between an arbitrary number of logical qubits, achieving all-to-all logical connectivity through coherent spin shuttling. We further propose an ancilla-sharing scheme that encodes multiple logical qubits within a single logical element, compressing the physical footprint of the processor and improving long-range gate fidelity. Extending the architecture from a one-dimensional bus to a two-dimensional grid of shuttling tracks reduces the inter-qubit distance, yielding consistent improvements in logical error. Finally, we apply the Quantum Reverse Mapping methodology at the logical level to optimize the layout of a \textit{15-to-1} magic state distillation circuit, demonstrating how the transversal capabilities of the proposed architecture can be leveraged for universal fault-tolerant computation. Taken together, these results establish a principled co-design framework that bridges the physical, error-correction, and logical computation layers of the quantum stack, and demonstrate that spin-qubit shuttling architectures are a viable and flexible substrate for scalable fault-tolerant quantum computation.
In this paper, we present a machine learning framework to design high-fidelity multi-qubit gates for quantum processors based on quantum dots in silicon, with qubits encoded in the spin of single electrons. In this hardware architecture, the control landscape is vast and complex, so we use the deep reinforcement learning method to design optimal control pulses to achieve high fidelity multi-qubit gates. In our learning model, a simulator models the physical system of quantum dots and performs the time evolution of the system, and a deep neural network serves as the function approximator to learn the control policy. We evolve the Hamiltonian in the full state-space of the system, and enforce realistic constraints to ensure experimental feasibility.
A two-qubit controlled-not (cnot) gate, realized by a controlled-phase (C-phase) gate combined with single-qubit gates, has been experimentally implemented recently for quantum-dot spin qubits in isotopically enriched silicon, a promising solid-state system for practical quantum computation. In the experiments, the single-qubit gates have been demonstrated with fault-tolerant control fidelity, but the infidelity of the two-qubit C-phase gate is, primarily due to the electrical noise, still higher than the required error threshold for fault-tolerant quantum computation (FTQC). Here, by taking the realistic system parameters and the experimental constraints on the control pulses into account, we construct experimentally realizable high-fidelity cnot gates robust against electrical noise with the experimentally measured 1/f1.01 noise spectrum and also against the uncertainty in the interdot tunnel coupling amplitude. Our fine-tuned optimal cnot gate has about two orders of magnitude improvement in gate infidelity over the ideal C-phase gate constructed without considering any noise effect. Furthermore, within the same control framework, high-fidelity and robust single-qubit gates can also be constructed, paving the way for large-scale FTQC.