There is currently a tremendous interest in developing practical applications of NISQ processors without the overhead required by full error correction. Quantum information processing is especially challenging within the gate model, as algorithms quickly lose fidelity as the problem size and circuit depth grow. This has lead to a number of non-gate-model approaches such as analog quantum simulation and quantum annealing. These approaches come with specific hardware requirements that are typically different than that of a universal gate-based quantum computer. We have previously proposed a non-gate-model approach called the single-excitation subspace (SES) method, which requires a complete graph of superconducting qubits. Like any approach lacking error correction, the SES method is not scalable, but it often leads to algorithms with constant depth, allowing it to outperform the gate model in a wide variety of applications. A challenge of the SES method is that it requires a physical qubit for every basis state in the computer's Hilbert space. This imposes large resource costs for algorithms using registers of ancillary qubits, as each ancilla would double the required graph size. Here we show how to circumvent this doubling by leaving the SES and reintroducing a tensor product structure in the computational subspace. Specifically, we implement the tensor product of an SES register holding ``data" with one or more ancilla qubits. This enables a hybrid form of quantum computation where fast SES operations are performed on the data, traditional logic gates and measurements are performed on the ancillas, and controlled-unitaries act between. As an application we give an SES implementation of the quantum linear system solver of Harrow, Hassidim, and Lloyd.
There is currently a tremendous interest in developing practical applications of NISQ processors without the overhead required by full error correction. Quantum information processing is especially challenging within the gate model, as algorithms quickly lose fidelity as the problem size and circuit depth grow. This has lead to a number of non-gate-model approaches such as analog quantum simulation and quantum annealing. These approaches come with specific hardware requirements that are typically different than that of a universal gate-based quantum computer. We have previously proposed a non-gate-model approach called the single-excitation subspace (SES) method, which requires a complete graph of superconducting qubits. Like any approach lacking error correction, the SES method is not scalable, but it often leads to algorithms with constant depth, allowing it to outperform the gate model in a wide variety of applications. A challenge of the SES method is that it requires a physical qubit for every basis state in the computer's Hilbert space. This imposes large resource costs for algorithms using registers of ancillary qubits, as each ancilla would double the required graph size. Here we show how to circumvent this doubling by leaving the SES and reintroducing a tensor product structure in the computational subspace. Specifically, we implement the tensor product of an SES register holding ``data" with one or more ancilla qubits. This enables a hybrid form of quantum computation where fast SES operations are performed on the data, traditional logic gates and measurements are performed on the ancillas, and controlled-unitaries act between. As an application we give an SES implementation of the quantum linear system solver of Harrow, Hassidim, and Lloyd.
Fusing the single-excitation subspace with C2n
There is a tremendous interest in developing practical applications for noisy intermediate-scale quantum processors without the overhead required by full error correction. Near-term quantum information processing is especially challenging within the standard gate model, as algorithms quickly lose fidelity as the problem size and circuit depth grow. This has lead to a number of non-gate-model approaches such as analog quantum simulation and quantum annealing. These come with specific hardware requirements that are different than that of a universal gate-based quantum computer. We have previously proposed an approach called the single-excitation subspace (SES) method, which uses a complete graph of superconducting qubits with tunable coupling. Without error correction the SES method is not scalable, but it offers several algorithmic components with constant depth, which is highly desirable for near-term use. The challenge of the SES method is that it requires a physical qubit for every basis state in the computer's Hilbert space. This imposes exponentially large resource costs for algorithms using registers of ancillary qubits, as each ancilla would double the required graph size. Here we show how to circumvent this doubling by leaving the SES and fusing it with a multi-ancilla Hilbert space. Specifically, we implement the tensor product of an SES register holding "data" with one or more ancilla qubits, which are able to independently control arbitrary [Formula: see text] unitary operations on the data in a constant number of steps. This enables a hybrid form of quantum computation where fast SES operations are performed on the data, traditional logic gates and measurements are performed on the ancillas, and controlled-unitaries act between. As example applications, we give ancilla-assisted SES implementations of quantum phase estimation and the quantum linear system solver of Harrow, Hassidim, and Lloyd.
Current quantum computing architectures lack the size and fidelity required for universal fault-tolerant operation, limiting the practical implementation of key quantum algorithms to all but the smallest problem sizes. In this work we propose an alternative method for general-purpose quantum computation that is ideally suited for such ``prethreshold'' superconducting hardware. Computations are performed in the n-dimensional single-excitation subspace (SES) of a system of n tunably coupled superconducting qubits. The approach is not scalable, but allows many operations in the unitary group SU(n) to be implemented by a single application of the Hamiltonian, bypassing the need to decompose a desired unitary into elementary gates. This feature makes large, nontrivial quantum computations possible within the available coherence time. We show how to use a programmable SES chip to perform fast amplitude amplification and phase estimation, two versatile quantum subalgorithms. We also show that an SES processor is well suited for Hamiltonian simulation, specifically simulation of the Schr\"odinger equation with a real but otherwise arbitrary $n\ifmmode\times\else\texttimes\fi{}n$ Hamiltonian matrix. We discuss the utility and practicality of such a universal quantum simulator, and propose its application to the study of realistic atomic and molecular collisions.
Quantum computation with a complete graph of superconducting qubits has been recently proposed, and applications to amplitude amplification, phase estimation, and the simulation of realistic atomic collisions given [Phys. Rev. A 91, 062309 (2015)]. This single-excitation-subspace (SES) approach does not require error correction and is practical now. Previously it was shown how to implement symmetric $n\ifmmode\times\else\texttimes\fi{}n$ unitaries in a single step, but not general unitaries. Here we show that any element in the unitary group U(n) can be executed in no more than three steps, for any n. This enables the implementation of highly complex operations in constant time and, in some cases, even allows for the compilation of an entire algorithm down to only three operations. By using this protocol we show how to prepare any pure state of an SES chip in three steps and also how to compute, for a given SES state $\ensuremath{\rho}$, the expectation value $\mathrm{Tr}(\ensuremath{\rho}O)$ of any $n\ifmmode\times\else\texttimes\fi{}n$ Hermitian observable O in a constant number of steps.
We describe an alternative approach to quantum computation that is ideally suited for today's sub-threshold-fidelity qubits, and which can be applied to a family of hardware models that includes superconducting qubits with tunable coupling. In this approach, the computation on an n-qubit processor is carried out in the n-dimensional single-excitation subspace (SES) of the full 2^n-dimensional Hilbert space. Because any real Hamiltonian can be directly generated in the SES [E. J. Pritchett et al., arXiv:1008.0701], high-dimensional unitary operations can be carried out in a single step, bypassing the need to decompose into single- and two-qubit gates. Although technically nonscalable and unsuitable for applications (including Shor's) requiring enormous Hilbert spaces, this approach would make practical a first-generation quantum computer capable of achieving significant quantum speedup.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Accurate and efficient implementation of parallel quantum gates is crucial for scalable quantum information processing. However, the unavoidable crosstalk between qubits in current noisy processors impedes the achievement of high gate fidelities and renders full Hilbert-space control optimization prohibitively difficult. Here, we overcome this challenge by reducing the full-system optimization to crosstalk-robust control over constant-sized subsystems, which dramatically reduces the computational cost. Our method effectively eliminates the leading-order gate operation deviations induced by crosstalk, thereby suppressing error rates. Within this framework, we construct analytical pulse solutions for parallel single-qubit gates and numerical pulses for parallel multi-qubit operations. We validate the proposed approach numerically across multiple platforms, including coupled nitrogen-vacancy centers, a nuclear-spin processor, and superconducting-qubit arrays with up to 200 qubits. As a result, the noise scaling is reduced from exponential to linear for parallel single-qubit gates, and an order-of-magnitude reduction is achieved for parallel multi-qubit gates. Moreover, our method does not require precise knowledge of crosstalk strengths and makes no assumption about the underlying qubit connectivity or lattice geometry, thereby establishing a scalable framework for parallel quantum control in large-scale quantum architectures.