Note: This preprint has been superseded by arXiv:1806.04318. Recent advances in nanotechnology have enabled researchers to control individual quantum mechanical objects with unprecedented accuracy, opening the door for both quantum and extreme-scale conventional computing applications. As these devices become larger and more complex, the ability to design them such that they can be simply controlled becomes a daunting and computationally infeasible task. Here, motivated by ideas from compressed sensing, we introduce a protocol for the Compressed Optimization of Device Architectures (CODA). It leads naturally to a metric for benchmarking device performance and optimizing device designs, and provides a scheme for automating the control of gate operations and reducing their complexity. Because CODA is computationally efficient, it is readily extensible to large systems. We demonstrate the CODA benchmarking and optimization protocols through simulations of up to eight quantum dots in devices that are currently being developed experimentally for quantum computation.
Note: This preprint has been superseded by arXiv:1806.04318. Recent advances in nanotechnology have enabled researchers to control individual quantum mechanical objects with unprecedented accuracy, opening the door for both quantum and extreme-scale conventional computing applications. As these devices become larger and more complex, the ability to design them such that they can be simply controlled becomes a daunting and computationally infeasible task. Here, motivated by ideas from compressed sensing, we introduce a protocol for the Compressed Optimization of Device Architectures (CODA). It leads naturally to a metric for benchmarking device performance and optimizing device designs, and provides a scheme for automating the control of gate operations and reducing their complexity. Because CODA is computationally efficient, it is readily extensible to large systems. We demonstrate the CODA benchmarking and optimization protocols through simulations of up to eight quantum dots in devices that are currently being developed experimentally for quantum computation.
Recent advances in nanotechnology allow very accurate manipulation of small collections of quantum dots (QDs), an important step in semiconductor-based quantum computation. As the number of QDs in a device grows, it becomes increasingly useful to control the system with as few voltage changes as possible. The authors offer a protocol, ``CODA'', both to efficiently identify sparse sets of voltage changes for controlling a quantum system, and to introduce a metric for comparing device designs. As a method for efficiently controlling $a\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}d$ designing a device, CODA will impact engineering solutions to the extension of semiconductor-based quantum computation.
Gate-defined quantum dots are a promising candidate system for realizing scalable, coupled qubit systems and serving as a fundamental building block for quantum computers. However, present-day quantum dot devices suffer from imperfections that must be accounted for, which hinders the characterization, tuning, and operation process. Moreover, with an increasing number of quantum dot qubits, the relevant parameter space grows sufficiently to make heuristic control infeasible. Thus, it is imperative that reliable and scalable autonomous tuning approaches are developed. This meeting report outlines current challenges in automating quantum dot device tuning and operation with a particular focus on datasets, benchmarking, and standardization. We also present insights and ideas put forward by the quantum dot community on how to overcome them. We aim to provide guidance and inspiration to researchers invested in automation efforts.
Arrays of quantum dots (QDs) are a promising candidate system to realize scalable, coupled qubit systems and serve as a fundamental building block for quantum computers. In such semiconductor quantum systems, devices now have tens of individual electrostatic and dynamical voltages that must be carefully set to localize the system into the single-electron regime and to realize good qubit operational performance. The mapping of requisite QD locations and charges to gate voltages presents a challenging classical control problem. With an increasing number of QD qubits, the relevant parameter space grows sufficiently to make heuristic control unfeasible. In recent years, there has been considerable effort to automate device control that combines script-based algorithms with machine learning (ML) techniques. In this Colloquium, a comprehensive overview of the recent progress in the automation of QD device control is presented, with a particular emphasis on silicon- and GaAs-based QDs formed in two-dimensional electron gases. Combining physics-based modeling with modern numerical optimization and ML has proven effective in yielding efficient, scalable control. Further integration of theoretical, computational, and experimental efforts with computer science and ML holds vast potential in advancing semiconductor and other platforms for quantum computing.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
As quantum devices make steady progress towards intermediate scale and fault-tolerant quantum computing, it is essential to develop rigorous and efficient measurement protocols that account for known sources of noise. Most existing quantum characterization protocols such as gate-set tomography and randomized benchmarking assume the noise acting on the qubits is Markovian. However, this assumption is often not valid, as for the case of 1/f charge noise or hyperfine nuclear spin noise. Here, we present a general framework for quantum process tomography (QPT) in the presence of time-correlated noise. We further introduce fidelity benchmarks that quantify the relative strength of different sources of Markovian and non-Markovian noise. As an application of our method, we perform a comparative theoretical and experimental analysis of silicon spin qubits. We first develop a detailed noise model that accounts for the dominant sources of noise and validate the model against experimental data. Applying our framework for time-correlated QPT, we find that the number of independent parameters needed to characterize one- and two-qubit gates can be compressed by 10× and 100× , respectively, when compared to the fully generic case. These compressions reduce the amount of tomographic measurements needed in experiment, while also significantly speeding up numerical simulations of noisy quantum circuit dynamics compared to time-dependent Hamiltonian simulation. Using this compressed noise model, we find good agreement between our theoretically predicted process fidelities and two-qubit interleaved randomized benchmarking fidelities of 99.8% measured in recent experiments on silicon spin qubits. More broadly, our formalism can be directly extended to develop efficient and scalable tuning protocols for high-fidelity control of large arrays of quantum devices with non-Markovian noise. Published by the American Physical Society 2024
Quantum information architecture (QIA) represents a paradigm shift in computational systems, offering unprecedented capabilities for data processing and quantum computation. Traditional optimization techniques often struggle to effectively adapt to the intricate and dynamic nature of QIA. This paper introduces a novel dynamic topology optimization algorithm designed specifically for QIA, leveraging the inherent properties of quantum information architectures to automatically adjust circuit configurations, leading to enhanced efficiency and adaptability. The core mechanism centers on employing quantum state transformations to dynamically reshape the qubit network, optimizing for specific computational objectives. This approach surpasses conventional methods by offering a level of automation and self-optimization not previously achievable, promising significant advancements in the design and implementation of quantum algorithms. We present a detailed analysis of the algorithm's performance and demonstrate its effectiveness through simulations and preliminary experiments.