We present a quantum CISC compiler and show how to assemble complex instruction sets in a scalable way. Enlarging the toolbox of universal gates by optimised complex multi-qubit instruction sets thus paves the way to fight decoherence for realistic settings. Compiling a quantum module into the machine code for steering a concrete quantum hardware device lends itself to be tackled by means of optimal quantum control. To this end, there are two opposite approaches: (i) one may use a decomposition into the restricted instruction set (RISC) of universal one- and two-qubit gates, which in turn have prefabricated translations into the machine code or (ii) one may prefer to generate the entire target module directly by a complex instruction set (CISC) of available controls. Here we advocate direct compilation up to the limit of system size a classical high-performance parallel computer cluster can reasonably handle. For going beyond these limits, i.e. for large systems we propose a combined way, namely (iii) to make recursive use of medium-sized building blocks generated by optimal control in the sense of a quantum CISC compiler. The advantage of the method over standard RISC compilations into one- and two-qubit universal gates is explored on the parallel cluster HLRB-II (with a total LINPACK performance of 63.3 TFlops/s) for the quantum Fourier transform, the indirect SWAP gate as well as for multiply-controlled CNOT gates. Implications for upper limits to time complexities are also derived.
We present a quantum CISC compiler and show how to assemble complex instruction sets in a scalable way. Enlarging the toolbox of universal gates by optimised complex multi-qubit instruction sets thus paves the way to fight decoherence for realistic settings. Compiling a quantum module into the machine code for steering a concrete quantum hardware device lends itself to be tackled by means of optimal quantum control. To this end, there are two opposite approaches: (i) one may use a decomposition into the restricted instruction set (RISC) of universal one- and two-qubit gates, which in turn have prefabricated translations into the machine code or (ii) one may prefer to generate the entire target module directly by a complex instruction set (CISC) of available controls. Here we advocate direct compilation up to the limit of system size a classical high-performance parallel computer cluster can reasonably handle. For going beyond these limits, i.e. for large systems we propose a combined way, namely (iii) to make recursive use of medium-sized building blocks generated by optimal control in the sense of a quantum CISC compiler. The advantage of the method over standard RISC compilations into one- and two-qubit universal gates is explored on the parallel cluster HLRB-II (with a total LINPACK performance of 63.3 TFlops/s) for the quantum Fourier transform, the indirect SWAP gate as well as for multiply-controlled CNOT gates. Implications for upper limits to time complexities are also derived.
The quantum instruction set (QIS) is defined as the quantum gates that are physically realizable by controlling the qubits in quantum hardware. Compiling quantum circuits into the product of the gates in a properly defined QIS is a fundamental step in quantum computing. We here propose the quantum variational instruction set (QuVIS) formed by flexibly designed multiqubit gates for higher speed and accuracy of quantum computing. The controlling of qubits for realizing the gates in a QuVIS is variationally achieved using the fine-grained time optimization algorithm. Significant reductions in both the error accumulation and time cost are demonstrated in realizing the swaps of multiple qubits and quantum Fourier transformations, compared with the compiling by a standard QIS such as the quantum microinstruction set (QuMIS, formed by several one- and two-qubit gates including one-qubit rotations and controlled-not gates). With the same requirement on quantum hardware, the time cost for QuVIS is reduced to less than one-half of that for QuMIS. Simultaneously, the error is suppressed algebraically as the depth of the compiled circuit is reduced. As a general compiling approach with high flexibility and efficiency, QuVIS can be defined for different quantum circuits and be adapted to the quantum hardware with different interactions.
Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of 5×, with a maximum of 10×. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.
The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical.
To move beyond these hurdles, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead.
We detail the hardware implementation to demonstrate the feasibility, in terms of both pulse control and calibration of this superior gate scheme on realistic hardware. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-ISA, SOTA compiler, and pulse implementation counterparts, in significantly reducing 2Q gate counts, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.
Advances in quantum algorithms as well as in control hardware designs are continuously being made. These quantum algorithms, expressed as quantum circuits, need to be translated to a set of instructions from a defined quantum instruction-set architecture (ISA), which are executed by the control hardware. These translations can be done by a compiler, targeting different qubit technologies. Specifically for diamond NV centers, no compiler exists to perform this translation. Therefore, in this paper we present a compiler designed for quantum computers utilizing diamond NV center specific instructions, such as direct carbon control and partial swaps, to reduce execution times and gate count. Additionally, our compiler adds on top of general compilers by allowing classical instructions to perform state tomography and measurement-based operations. The output of the compiler is tested in a diamond NV center specific simulator. Comparing a general compiler output with the diamond NV center specific output of our compiler while applying decoherence and depolarization noise showed reduced noise effects due to diamond specific decomposition. The compiler was also tested to perform state tomography and measurement-based operations, which showed to be functional. Our results show that we have successfully created a compiler with integrated classical and quantum instructions support, which can improve circuit execution fidelity by utilizing diamond specific optimizations.
Complex instruction set computing architecture for performing accurate quantum Z rotations with less magic
We present quantum protocols for executing arbitrarily accurate π/2k rotations of a qubit about its Z axis. Reduced instruction set computing (\textsc{risc}) architectures typically restrict the instruction set to stabilizer operations and a single non-stabilizer operation, such as preparation of a "magic" state from which T=Z(π/4) gates can be teleported. Although the overhead required to distill high-fidelity copies of this magic state is high, the subsequent quantum compiling overhead to realize Z rotations in a \textsc{risc} architecture can be much greater. We develop a complex instruction set computing (\textsc{cisc}) architecture whose instruction set includes stabilizer operations and preparation of magic states from which Z(π/2k) gates can be teleported, for 2≤k≤kmax. This results in a substantial overall reduction in the number of gates required to achieve a desired gate accuracy for Z rotations. The key to our construction is a family of shortened quantum Reed-Muller codes of length 2k+2−1, whose magic-state distillation threshold shrinks with k but is greater than 0.85% for k≤6.
The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.