Efficient decoder design for error correction codes

Chenrong Xiong

Ekta Sharma, Ismail Shakeel, Ravinesh Chand Deo +2 more

The development of computationally-efficient algorithms is crucial to support the extremely-low latency and ultra-high reliability requirements of the next-generation radio communication systems. Error-correction codes (ECC) are used in communication systems to maintain the reliability of data transmissions. In this paper, several commonly used artificial intelligence (AI) methods are used to design algorithms for bitwise decoding of (ECC). The AI-based decoding algorithms are analysed and compared using their error-correction performance, training time and computational intensity. The efficacy is assessed using the benchmark codes: extended binary Golay and the Hamming code for varying Signal-to-Noise Ratios (SNR) over the Additive White Gaussian Noise (AWGN) channel and the decoding performance is evaluated using the block error rate (BLER). It is envisaged that the results from this comparative study would help to identify AI models most suitable for developing computationally efficient and practically-implementable algorithms for decoding longer ECC.

Jun Ting Lin

Yoni Choukroun, Lior Wolf

Error correction codes are a crucial part of the physical communication layer, ensuring the reliable transfer of data over noisy channels. The design of optimal linear block codes capable of being efficiently decoded is of major concern, especially for short block lengths. While neural decoders have recently demonstrated their advantage over classical decoding techniques, the neural design of the codes remains a challenge. In this work, we propose for the first time a unified encoder-decoder training of binary linear block codes. To this end, we adapt the coding setting to support efficient and differentiable training of the code for end-to-end optimization over the order two Galois field. We also propose a novel Transformer model in which the self-attention masking is performed in a differentiable fashion for the efficient backpropagation of the code gradient. Our results show that (i) the proposed decoder outperforms existing neural decoding on conventional codes, (ii) the suggested framework generates codes that outperform the {analogous} conventional codes, and (iii) the codes we developed not only excel with our decoder but also show enhanced performance with traditional decoding techniques.

Esa Alghonaim

Low Density Parity Check (LDPC) codes are considered to be one of the best classes of error-correcting codes. This thesis deals with two major issues in LDPC codes: decoder design to enhance error correction performance and efficient decoder implementation. Five techniques have been introduced in this thesis. First, an efficient platform for LDPC code design and performance evaluation is developed. This platform implements parallel simulation algorithms to efficiently evaluate the performance of the proposed algorithms for LDPC decoders and code design. Second, an innovative technique is introduced to improve the performance of LDPC decoding in the error-floor region. Special structures in the code graph, called trapping sets, are considered to be the major source of decoding errors in the error-floor region. The proposed technique is based on eliminating the negative effect of trapping sets during LDPC decoding. As a third contribution, a novel approach to improve the decoder performance and/or throughput is introduced. This approach is based on utilizing LDPC decoder idle times by introducing two queues: one at the decoder input and the other at the decoder output. This architecture enables the decoder to run extra iterations beyond the conventional maximum allowable iterations. The fourth proposed technique reduces the bit error rate of LDPC decoders. This technique is based on tracking the number of failed parity check equations in the intermediate decoding iterations, rather than only relying on the final decoder output (after reaching the maximum number of iterations). The last proposed technique deals with the construction of interconnect efficient fully-parallel LDPC codes with high error correction performance. Fully-parallel implementation is very hard due to the complexity of processing elements interconnections. The proposed technique is based on constructing LDPC codes with less complex interconnections and with low impact on the error correction performance. This goal is achieved by putting a constraint on the maximum connection length between any two processing elements.

Yibin Ng, Wai Ho Mow