Effective qubit mapping facilitates quantum algorithm implementations in physical quantum computing architectures. Recent work reported promising qubit mapping on one-dimensional trapped-ion systems. Due to manufacturing complexity, however, it is insufficient to map all logical qubits into one single qubit array in a large-scale quantum circuit; instead, we shall divide a quantum circuit into subcircuits for extending to two-dimensional trapped-ion systems. Nevertheless, operating a two-qubit gate between different subcircuits reduces the circuit fidelity. As a result, it is desirable to develop an effective partitioning algorithm that can maintain fidelity and minimize the execution time. This paper develops an effective divide-and-conquer algorithm for each array. Unlike traditional min-cut partitioning to balance the qubit number on each array, we propose a depth-aware partitioning algorithm to expand the solution space for all mapping solutions and optimize the execution time on each array. Besides, we develop a satisfiability modulo theories-based algorithm to optimize the mapping solution for each array. Experimental results show that our algorithm can averagely achieve a 14% total time step reduction and a 30% total fidelity improvement for commonly used benchmarks.
Effective qubit mapping facilitates quantum algorithm implementations in physical quantum computing architectures. Recent work reported promising qubit mapping on one-dimensional trapped-ion systems. Due to manufacturing complexity, however, it is insufficient to map all logical qubits into one single qubit array in a large-scale quantum circuit; instead, we shall divide a quantum circuit into subcircuits for extending to two-dimensional trapped-ion systems. Nevertheless, operating a two-qubit gate between different subcircuits reduces the circuit fidelity. As a result, it is desirable to develop an effective partitioning algorithm that can maintain fidelity and minimize the execution time. This paper develops an effective divide-and-conquer algorithm for each array. Unlike traditional min-cut partitioning to balance the qubit number on each array, we propose a depth-aware partitioning algorithm to expand the solution space for all mapping solutions and optimize the execution time on each array. Besides, we develop a satisfiability modulo theories-based algorithm to optimize the mapping solution for each array. Experimental results show that our algorithm can averagely achieve a 14% total time step reduction and a 30% total fidelity improvement for commonly used benchmarks.
Qubit mapping is crucial in optimizing the performance of quantum algorithms for physical executions on quantum computing architectures. Many qubit mapping algorithms have been proposed for superconducting systems recently. However, due to their limitations on the physical qubit connectivity, costly SWAP gates are often required to swap logical qubits for proper quantum operations. Trapped-ion systems have emerged as an alternative quantum computing architecture and have gained much recent attention due to their relatively long coherence time, high-fidelity gates, and good scalability for multi-qubit coupling. However, the qubit mapping of the new trapped-ion systems remains a relatively untouched research problem. This paper proposes a new coupling constraint graph with multi-pin nets to model the unique constraints and connectivity patterns in one-dimensional trapped-ion systems. To minimize the time steps for quantum circuit execution satisfying the coupling constraints for trapped-ion systems, we devise a divide-and-conquer solution using Satisfiability Modulo Theories for efficient qubit mapping on trapped-ion quantum computing architectures. Experimental results demonstrate the superiority of our approach in scalability and effectiveness compared to the previous work.
Trapped-ion (TI) quantum computer is one of the forerunner quantum technologies. Execution of a quantum gate in multiple trap TI system may frequently involve ions from two different traps, hence one of the ions needs to be shuttled (moved) between traps to be co-located, degrading fidelity, and increasing the program execution time. The choice of initial mapping influences the number of shuttles. The existing Greedy policy neglects the depth of the program at which a gate is present. Intuitively, the contribution of the late-stage gates to the initial mapping is less since the ions might have already shuttled to a different trap to satisfy other gate operations. In this paper, we target this gap and propose a new program adaptive policy especially for programs with considerable depth and high number of qubits (valid for practical-scale quantum programs). Our technique achieves an average reduction of 9% shuttles/program (with 21.3% at best) for 120 random circuits and enhances the program fidelity up to 3.3X (1.41X on average).
Abstract The circuit model of a quantum computer consists of sequences of gate operations between quantum bits (qubits), drawn from a universal family of discrete operations1. The ability to execute parallel entangling quantum gates offers efficiency gains in numerous quantum circuits2–4, as well as for entire algorithms—such as Shor’s factoring algorithm5—and quantum simulations6, 7. In circuits such as full adders and multiple-control Toffoli gates, parallelism can provide an exponential improvement in overall execution time through the divide-and-conquer technique8. More importantly, quantum gate parallelism is essential for fault-tolerant error correction of qubits that suffer from idle errors9, 10. However, the implementation of parallel quantum gates is complicated by potential crosstalk, especially between qubits that are fully connected by a common-mode bus, such as in Coulomb-coupled trapped atomic ions11, 12 or cavity-coupled superconducting transmons13. Here we present experimental results for parallel two-qubit entangling gates in an array of fully connected trapped 171Yb+ ion qubits. We perform a one-bit full-addition operation on a quantum computer using a depth-four quantum circuit4, 14, 15, where circuit depth denotes the number of runtime steps required. Our method exploits the power of highly connected qubit systems using classical control techniques and will help to speed up quantum circuits and achieve fault tolerance in trapped-ion quantum computers.
Quantum computers are superior to existing classical supercomputers in terms of run time for specific tasks, and various studies on quantum computers are in progress. Despite this, there is a significant gap in technology between available technologies and actual quantum computers on the noisy intermediate-scale quantum-scale. Currently, various quantum algorithms have been implemented and verified using quantum simulations. Therefore, the runtime performance of a quantum circuit can be verified in the same environment as a real quantum machine. A quantum compiler compiles quantum circuits. When a quantum circuit is compiled, logical qubits in a quantum circuit should be mapped to physical qubits, called qubit mapping. As qubit mapping is an NP-Complete problem, the compilation time increases exponentially according to the number of qubits. Therefore, various studies on effective qubit mapping techniques have been developed to accelerate the execution time. This paper proposes a new parallelized Qubit mapping algorithm. The proposed method consists of three-step processes: one circuit is divided into several circuits; the SABRE enhanced algorithm is executed on each circuit in parallel and then merged. The performance was evaluated using 10 benchmarks. The experimental results revealed an acceleration of up to 6.42x and an average speed up of 4.8x, with an average overhead of 1.03x in terms of the number of gates obtained. The proposed method outperformed the well-known modern qubit-mapping algorithm in terms of the execution time with exponential speedup improvement.
The Quantum Charge Coupled Device (QCCD) architecture is a promising pathway toward scalable quantum computation in trapped-ion quantum computers. Devices using this architecture rely on efficient ion shuttling between memory and processing zones to execute quantum circuits. Hardware for trapped-ion quantum computers with multiple different zones is already being developed, but without proper compilation support, there is a risk that we will not be able to use their full potential. Recent approaches to shuttling algorithms have primarily focused on small architectures or devices with a single processing zone. In this work, we propose to extend these algorithms to large grid-type systems with multiple processing zones embedded in the memory zone. For that, a two-step solution is described: first, partitioning quantum circuits to determine where each gate is executed, and second, adapting a publicly available shuttling algorithm for architectures with a single processing zone to handle the increased complexity of multi-zone systems. Empirical evaluations demonstrate the method's effectiveness across a range of grid-type architectures, showing that additional processing zones can significantly reduce quantum circuit execution time. With that, we provide a foundation for the compilation of shuttling-based trapped-ion quantum computers with multiple processing zones. An open-source implementation of the proposed approach is available at https://github.com/cda-tum/mqt-ion-shuttler.
Because of the largest number of qubits available, and the massive parallel execution of entangling two-qubit gates, atom arrays is a promising platform for quantum computing. The qubits are selectively loaded into arrays of optical traps, some of which can be moved during the computation itself. By adjusting the locations of the traps and shining a specific global laser, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. In comparison, previous QC architectures only generate entanglement on a fixed set of quantum register pairs. Thus, reconfigurable atom arrays (RAA) present a new challenge for QC compilation, especially the qubit mapping/layout synthesis stage which decides the qubit placement and gate scheduling. In this paper, we consider an RAA QC architecture that contains multiple arrays, supports 2D array movements, represents cutting-edge experimental platforms, and is much more general than previous works. We start by systematically examining the fundamental constraints on RAA imposed by physics. Built upon this understanding, we discretize the state space of the architecture, and we formulate layout synthesis for such an architecture to a satisfactory modulo theories problem. Finally, we demonstrate our work by compiling the quantum approximate optimization algorithm (QAOA), one of the promising near-term quantum computing applications. Our layout synthesizer reduces the number of required native two-qubit gates in 22-qubit QAOA by 5.72x (geomean) compared to leading experiments on a superconducting architecture. Combined with a better coherence time, there is an order-of-magnitude increase in circuit fidelity.