We tried to find quantum advantage. Here are the six things we got wrong: A feasibility study of output-aware tensor-network contraction against real quantum hardware
A feasibility study testing whether quantum circuits can be constructedwhere exact classical simulation cost grows much faster than the physicalcircuit depth needed to run them, using output-aware tensor-networkcontraction validated against two real IBM Quantum hardware jobs(dadm3mjdd5gc73d7gvjg, dadm9qdnj4cs73ae2teg; 40,960 shots total). The honest conclusion is no — not on any hardware available today. Reachingthat conclusion required correcting the study's own conclusions six times;those corrections, and the measurements behind them, are the primarycontribution. Key measured results: classical contraction cost scales as 2^w withmeasured exponent 1.984; effective two-qubit error on IBM's Heronarchitecture is gate-local at 0.845%, reproducible across two independentjobs; memory is not a binding constraint once slicing is applied (1.00-3.18xFLOP penalty); connectivity degree, not planarity, is the dominanttopological lever; standard error suppression (dynamical decoupling +twirling) made fidelity worse on this circuit class; qubit count sets a hardceiling on achievable classical hardness (2^n). This is a feasibility study, not an advantage claim: no quantum advantage,no novel algorithm (frontier contraction is textbook variable elimination),and no verified large-width result are claimed. Full reproducibility scriptsincluded.
A feasibility study testing whether quantum circuits can be constructedwhere exact classical simulation cost grows much faster than the physicalcircuit depth needed to run them, using output-aware tensor-networkcontraction validated against two real IBM Quantum hardware jobs(dadm3mjdd5gc73d7gvjg, dadm9qdnj4cs73ae2teg; 40,960 shots total). The honest conclusion is no — not on any hardware available today. Reachingthat conclusion required correcting the study's own conclusions six times;those corrections, and the measurements behind them, are the primarycontribution. Key measured results: classical contraction cost scales as 2^w withmeasured exponent 1.984; effective two-qubit error on IBM's Heronarchitecture is gate-local at 0.845%, reproducible across two independentjobs; memory is not a binding constraint once slicing is applied (1.00-3.18xFLOP penalty); connectivity degree, not planarity, is the dominanttopological lever; standard error suppression (dynamical decoupling +twirling) made fidelity worse on this circuit class; qubit count sets a hardceiling on achievable classical hardness (2^n). This is a feasibility study, not an advantage claim: no quantum advantage,no novel algorithm (frontier contraction is textbook variable elimination),and no verified large-width result are claimed. Full reproducibility scriptsincluded.
We classically simulate the IBM doped Clifford random circuit sampling experiment, comprising 70 qubits, 70 entangling layers, and 468 inserted T gates, as reported in the first version of arXiv:2607.25941. A deterministic temporal-boundary tensor network contraction approach is specifically designed to tackle such open-boundary one-dimensional brickwork circuits with operator-Schmidt-rank-2 entangling gates. For an n-qubit circuit of depth d, the resulting unsliced path evaluates an exact amplitude with contraction width ⌈d/2⌉; Ratcatcher calculations certify that no smaller width is possible for the tested instances. Because one-qubit gates are absorbed without changing the network topology, the width and dense scheduled contraction cost are independent of their values and of the number and placement of T gates. For this initial instance, its largest intermediate tensor contains 235 complex64 entries (256 times smaller than IBM's estimation), corresponding to a tensor payload of 256 GiB, and is distributed across eight GPUs within a node. Using 32 nodes, with eight NVIDIA H100 GPUs per node, we completed all 2051 amplitude batches corresponding to IBM's published output bitstrings in 37.3 minutes. The resulting probabilities yield a log-XEB estimate of 0.35034 with a 95% interval of [0.29763,0.40305]. Under the Porter--Thomas and scrambled-noise assumptions, this is numerically compatible with IBM's fidelity lower bound; separately, fidelity-weighted resource accounting projects a 583-contraction workload with a 10.6-minute makespan on the same 32 nodes. More broadly, the approach provides a practical diagnostic for experimental outputs and a quantitative tool for designing future doped Clifford sampling experiments.
We report forward random-circuit sampling (RCS) on the 120-qubit Nighthawk r2 superconducting processor (ibm_phoenix) with square-lattice connectivity, using 61 qubits, native CZ gates, and the standard cloud execution stack with no benchmark-specific calibration. Two independent fidelity estimators---mirror benchmarking and three- and four-patch cross-entropy benchmarking (XEB)---agree with each other at every measured depth, the mirror from 4 to 40 cycles and the patched estimators from 20 to 40 cycles, across more than two orders of magnitude of fidelity decay, and exceed the first-generation Nighthawk r1 device by more than an order of magnitude at fixed depth. The 36-cycle circuits sit at the depth where tensor-network contraction cost saturates at system size: a contraction-cost estimator validated against the published Sycamore and Zuchongzhi networks places the single-amplitude cost at ∼1022 complex operations. At FXEB(36)=2.3×10−3 under favorable memory assumptions this implies 1.2×1027 machine operations within the bounded-fidelity rejection-sampling model --- more than a century of runtime on the Frontier supercomputer --- to collect a 106-sample ensemble, which takes only 19\,s on Nighthawk r2. To our knowledge, this is the first demonstration of quantum advantage for a vanilla random-circuit sampling on a commercially and broadly accessible quantum processor that most non-expert quantum computer users can easily replicate.
Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark.
Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, Fest. For MDKP and MIS, an empirical operating point near Fest≈0.1, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction 10!/2100 at n=10; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below Fest=10−3. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.
Peaked quantum circuits, whose output distribution is sharply concentrated on a single bitstring, have emerged as a promising candidate for verifiable quantum advantage, as the correctness of the quantum output can be checked by simply comparing against the known peak. Recent work by Gharibyan et al. arXiv:2510.25838 claimed heuristic quantum advantage using peaked circuits executed on Quantinuum's 56-qubit H2 processor. These peaked circuits concentrate their output on a single hidden bitstring by training a shallow simulable circuit variationally and inserting an obfuscated permutation to increase the depth to a level that makes classical simulation intractable, with estimated runtimes of years for the largest instances. We show that these circuits can be efficiently simulated classically. We describe a method that efficiently performs a full tensor network contraction, allowing near-exact sampling and extraction of the peaked bitstring. The method exploits the mirrored structure of the circuit and iteratively cancels both halves into a Matrix Product Operator (MPO), and avoids the obfuscated permutation by greedily reducing the MPO bond dimension through a process we call unswapping. The method can fully contract and extract the peak of the largest circuit in approximately one hour on a single GPU, around half the time it took to run on the quantum hardware.
We review the recent quantum advantage experiments by IBM, D-Wave, and Google, focusing on cases where efficient classical simulations of the experiment were demonstrated or attempted using tensor network methods. We assess the strengths and limitations of these tensor network-based approaches and examine how the interplay between classical simulation and quantum hardware has advanced both fields. Our goal is to clarify what these results imply for the next generation of quantum advantage experiments. We identify regimes and system features that remain challenging for current tensor network approaches, and we outline directions where improved classical methods could further raise the standard for claiming quantum advantage. By analyzing this evolving competition, we aim to provide a clear view of where genuine, scalable quantum advantage is most likely to emerge.
Tensor-network contraction simulates quantum circuits, but modern matrix accelerators (NPUs, TPUs) expose only real GEMM pipelines, so the complex networks of quantum simulation must be reconstructed in software. We resolve the mismatch by a realification rewrite that maps any complex tensor network to a real one. At each merge of two complex tensors, a rank-3 structure tensor realizes Gauss's three-multiplication (3M) formula; contractions with one or no complex operand need only two or one real products. We prove a tight cost law: overhead 1+2m+r in real multiplications, where m and r are the volume fractions of two- and one-complex-operand contractions, never exceeding 3× relative to real contraction, with every intermediate at most doubled in size. On 67 circuits (random, Clifford+T, QAOA, VQE), the law holds across the real-to-complex range and complex-gate placement, not count, governs cost. Contraction orders transfer from the complex network with a relative arithmetic-cost gap below 5×10−4 on 66 of 67 circuits; the exception closes under a few steps of low-temperature simulated annealing. On an Ascend 910 NPU the rewrite beat both the four-real-GEMM baseline and a per-GEMM Gauss lowering on all twelve random circuits and on 52 of 55 structured cells (three cells slower by at most 12\%); the four-GEMM baseline was slower by a median 1.7× (random) and 1.4× (structured). Realification makes complex tensor-network contraction native to real-only matrix engines.