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International Conference on Communications

Deep Reinforcement Learning Aided Scheduling Design for Pipelined Layered QC-LDPC Decoder

Xia An, Chao Zhang, Jian Song, Jintao Wang

Published May 24, 2026• 0 citations
Publisher
DOI
10.1109/icc59461.2026.11587464

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For multi-edge type quasi-cyclic low-density parity-check (MET-QC-LDPC) codes, the presence of common variable nodes shared between rows within a single layer poses great challenges for the hardware design of the decoder. In this study, a cross-layer update scheduling method for pipelined layered MET-QC-LDPC codes is proposed to achieve improved conflict resolution. Through a probabilistic analysis, we show that by pairing layers with relatively small common degrees and performing alternating updates between the paired layers, better conflict resolution can be achieved than the layer-by-layer updating approach. Experimental results demonstrate that, at medium to low code rates, 50% to 75% of memory conflicts can be mitigated through the proposed cross-layer scheduling compared to the layer-by-layer scheduling approach, without compromising decoding performance.
In this study, a scheduling policy of layered decoding for quasi-cycle (QC) low-density parity-check (LDPC) codes with high throughput and good performance is designed. The influence of scheduling on the delay of the decoder's hardware implementation and on the decoding performance are considered simultaneously. Specifically, we analyze the idle time required under various scheduling sequences within a pipelined decoding architecture and formulate the problem as a traveling salesman problem (TSP) aiming at minimizing idle time. Furthermore, considering that different scheduling sequences can affect decoding performance, we refine the graph used to solve the TSP based on scheduling characteristics that promote improved decoding outcomes. Simulation results demonstrate that the identified scheduling sequence achieves a low number of hardware delays while maintaining excellent decoding performance for 5G New Radio (NR) LDPC codes.
Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%-109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.