Low-density parity-check (LDPC) codes have been selected as the channel coding scheme for 5G NR standard, which have excellent performance approaching the Shannon limit and are easy to implement in hardware. The decoding algorithm and scheduling scheme of LDPC codes have a significant impact on performance. The row degree (RD) and the number of punctured bits (PBs) are widely used to determine the update order of layers. In this letter, we used Matlab to simulate the error performance of the 5G LDPC codes. We completed the bit error rate and frame error rate simulations of six different decoding algorithms, including flooding LLR-BP, flooding NMS, layered LLR-BP, layered NMS, the lowest degree and least-punctured (LD-LP) layered LLR-BP and LD-LP layered NMS methods, for the 5G LDPC code with a base graph of size [46, 68], code rate 1/3, and code length of 1584.We further compared the performance of LD-LP layered decoding and LP-LD layered decoding. Moreover, we simulated the error performance of the core part of the LDPC code, which consists of four layers. We evaluated the effect of the update order of the four layers on the error performance of the code, and concluded that some update orders might give slightly better error performance than others.

International Conference on Computer and Communication Systems (ICCCS)Apr 19, 20244 citations

Accelerering av LDPC-avkodning på NVIDIA-GPUer : Prestandautvärdering med hjälp av Sionna-simuleringsramverket för 5G NR

Savira Ijaz

This thesis investigates the acceleration of Low-Density Parity-Check (LDPC) decoding for 5G New Radio (5G NR) communication systems using NVIDIA Graphics Processing Units (GPUs) and the NVIDIA Sionna simulation framework. LDPC codes are widely used in modern wireless communication systems, including 5G NR, because of their strong error-correction capabilities. However, the decoding process is computationally intensive since it relies on iterative algorithms that require multiple rounds of calculations before a final decoding decision can be made. As communication systems continue to demand higher data rates and lower latency, improving the efficiency of LDPC decoding has become increasingly important. A complete LDPC-based communication system was implemented using Sionna. The system included Cyclic Redundancy Check (CRC) encoding, LDPC encoding, modulation, transmission through an Additive White Gaussian Noise (AWGN) channel, demodulation, LDPC decoding, and CRC decoding. Three LDPC decoding algorithms were evaluated: Sum-Product Algorithm (SPA), Min-Sum Algorithm (MSA), and Offset Min-Sum Algorithm (OMSA). The study focused on measuring decoding performance on NVIDIA GPUs and investigating optimization techniques that could reduce LDPC decoding execution time while maintaining reliable decoding performance. Two optimization techniques were implemented and evaluated: CRC-based early termination and Accelerated Linear Algebra (XLA) graph compilation. Early termination allowed the LDPC decoder to stop before reaching the maximum number of decoding iterations. XLA was used to improve the efficiency of the computations executed during LDPC decoding. The performance of the optimized implementations was compared with a baseline implementation across different signal-to-noise ratio (SNR) values. The results showed that both optimization techniques reduced decoding execution time, while maintaining reliable Block Error Rate (BLER) performance compared to the baseline scheme.

Jan 1, 20260 citations