In order to characterize and calibrate quantum processing devices, a large amount of measurement data has to be collected.Active qubit reset increases the speed at which data can be gathered but requires additional hardware and/or calibration.The experimental apparatus can, however, be operated at elevated repetition rates without reset.In this case, the outcome of a first measurement serves as the initial state for the next experiment.Rol et al. have used this restless operation mode to accelerate the calibration of a single-qubit gate by measuring fixed-length sequences of Clifford gates that compose to X gates [Phys.Rev. Appl.7, 041001 (2017)].However, we find that when measuring pulse sequences that compose to arbitrary operations, distortion appears in the measured data.Here, we extend the restless methodology by showing how to efficiently analyze restless measurements and correct distortions to achieve an identical outcome and accuracy as compared to measurements in which the superconducting qubits are reset.This allows us to rapidly characterize and calibrate qubits.We illustrate this bias-corrected restless measurements method by measuring a Rabi oscillation at a 250 kHz repetition rate without any reset, for a qubit with a decay rate of 1/2π T 1 = 3 kHz.We also show that we can measure a single-and a two-qubit average gate fidelity using randomized benchmarking 20 and 8 times faster, respectively, than measurements that reset the qubits through T 1 decay.
Fast, high-fidelity qubit initialization is a key primitive for scalable quantum information processing, but conventional reset protocols either require long relaxation times or discard information contained in continuous measurement records. We demonstrate an adaptive measurement-based reset protocol for superconducting qubits that uses Bayesian inference to update the qubit-state estimate after each readout and dynamically adjust the feedback threshold. Unlike fixed-threshold or repeat-until-success (RUS) protocols, the method utilizes the full analog measurement history, enabling the reset decision to become progressively more conservative as confidence in ground-state preparation increases. Implemented with real-time FPGA-based feedback on a dispersively readout transmon qubit, the protocol achieves a ground-state initialization fidelity of
99.44±0.04% after a small number of reset rounds. We further compare adaptive reset with RUS strategies in multi-qubit experiments and show that adaptive thresholding provides deterministic reset duration while maintaining a five-qubit simultaneous-reset fidelity of
98.78±0.19%. These results establish Bayesian adaptive thresholding as a practical and scalable route to fast qubit reset in superconducting quantum processors.
Efficient qubit reset and leakage reduction are essential for scalable superconducting quantum computing, particularly in the context of quantum error correction. However, such operations often require additional on-chip components. Here, we propose and experimentally demonstrate a hardware-efficient approach to qubit reset and readout using a multi-mode Purcell filter in a superconducting quantum circuit. We exploit the inherent multi-mode structure of a coplanar waveguide resonator, using its fundamental and second-order modes for qubit reset and readout, respectively, thereby avoiding additional components. Implemented in a flip-chip architecture, our device achieves unconditional reset with residual excitation below 1\% in 220 ns, and a leakage reduction unit that selectively resets the second excited state within 62 ns with a residual
∣f⟩ population of 6.1\%, accounting for the readout error. Despite the qubits being directly coupled to the filter in our configuration, the measured relaxation times are not degraded owing to intrinsic Purcell protection provided by an auxiliary mode. To our knowledge, this is the first experimental trial that exploits different-order modes of a microwave resonator for distinct qubit operations, representing a new direction toward scalable, hardware-efficient quantum processor design.