Hybrid quantum-classical algorithms rely on iterative data exchange between quantum circuit execution and classical post-processing. As the quantum circuit size increases, communication and computation latencies within these exchanges become a critical system bottleneck. In this work, we present a system-level latency characterization of a hybrid quantumclassical learning workflow implemented on a cost-effective embedded system-on-chip (SoC). We evaluate a heterogeneous execution model where the quantum forward pass is executed on either local simulator or actual Quantum Processing Unit (QPU), while classical post-processing functions such as loss computation, gradient estimation, and parameter updates are accelerated on a low-latency Field-Programmable Gate Array (FPGA) pipeline. We measure end-to-end iteration latency for quantum machine learning circuits ranging from 4 to 14 qubits, investigating CPU-FPGA and QPU-FPGA workflows. Our findings provide a performance blueprint for future design and integration of low-latency embedded systems with utility-scale quantum computing systems.
Hybrid quantum-classical algorithms rely on iterative data exchange between quantum circuit execution and classical post-processing. As the quantum circuit size increases, communication and computation latencies within these exchanges become a critical system bottleneck. In this work, we present a system-level latency characterization of a hybrid quantumclassical learning workflow implemented on a cost-effective embedded system-on-chip (SoC). We evaluate a heterogeneous execution model where the quantum forward pass is executed on either local simulator or actual Quantum Processing Unit (QPU), while classical post-processing functions such as loss computation, gradient estimation, and parameter updates are accelerated on a low-latency Field-Programmable Gate Array (FPGA) pipeline. We measure end-to-end iteration latency for quantum machine learning circuits ranging from 4 to 14 qubits, investigating CPU-FPGA and QPU-FPGA workflows. Our findings provide a performance blueprint for future design and integration of low-latency embedded systems with utility-scale quantum computing systems.
Hybrid quantum–classical (HQC) computing refers to the approach of executing algorithms coherently on both quantum and classical resources. This approach makes the best use of current or near-term quantum computers by sharing the workload with classical high-performance computing. However, HQC algorithms often require a back-and-forth exchange of data between quantum and classical processors, causing system bottlenecks and leading to high latency in applications. The objective of this study is to investigate novel frameworks that unify quantum and reconfigurable resources for HQC and mitigate system bottleneck and latency issues. In this paper, we propose a reconfigurable framework for hybrid quantum–classical computing. The proposed framework integrates field-programmable gate arrays (FPGAs) with quantum processing units (QPUs) for deploying HQC algorithms. The classical subroutines of the algorithms are accelerated on FPGA fabric using a high-throughput processing pipeline, while quantum subroutines are executed on the QPUs. High-level software is used to seamlessly facilitate data exchange between classical and quantum workloads through high-performance channels. To evaluate the proposed framework, an HQC algorithm, namely variational quantum classification, and the MNIST dataset are used as a test case. We present a quantitative comparison of the proposed framework with a state-of-the-art quantum software framework running on a server-grade CPU. The results demonstrate that the FPGA pipeline achieves up to 8× improvement in runtime compared to the CPU baseline.
Embedded quantum machine learning (EQML) seeks to bring quantum machine learning (QML) capabilities to resource-constrained edge platforms such as IoT nodes, wearables, drones, and cyber-physical controllers. In 2026, EQML is technically feasible only in limited and highly experimental forms: (i) hybrid workflows where an embedded device performs sensing and classical processing while offloading a narrowly scoped quantum subroutine to a remote quantum processing unit (QPU) or nearby quantum appliance, and (ii) early-stage "embedded QPU" concepts in which a compact quantum co-processor is integrated with classical control hardware. A practical bridge is quantum-inspired machine learning and optimisation on classical embedded processors and FPGAs. This paper analyses feasibility from a circuits-and-systems perspective aligned with the academic community, formalises two implementation pathways, identifies the dominant barriers (latency, data encoding overhead, NISQ noise, tooling mismatch, and energy), and maps them to concrete engineering directions in interface design, control electronics, power management, verification, and security. We also argue that responsible deployment requires adversarial evaluation and governance practices that are increasingly necessary for edge AI systems.
Quantum computers are often treated as experimental add-ons that are loosely coupled to classical infrastructure through high-level interpreted languages and cloud-like orchestration. However, future deployments in both, high-performance computing (HPC) and embedded environments, will demand tighter integration for lower latencies, stronger determinism, and architectural consistency, as well as to implement error correction and other tasks that require tight quantum-classical interaction as generically as possible. We propose a vertically integrated quantum systems architecture that treats quantum accelerators and processing units as peripheral system components. A central element is the Quantum Abstraction Layer (QAL) at operating system kernel level. It aims at real-time, low-latency, and high-throughput interaction between quantum and classical resources, as well as robust low-level quantum operations scheduling and generic resource management. It can serve as blueprint for orchestration of lowlevel computational components “around” a QPU (and inside a quantum computer), and across different modalities. We present first results towards such an integrated architecture, including a virtual QPU model based on QEMU. The architecture is validated through functional emulation on three base architectures (x86_64, ARM64, and RISC-V), and timingaccurate FPGA-based simulations. This allows for a realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the ground for a system-level co-design methodology tailored for the next generation of quantum-classical computing.
In hybrid quantum-classical (HQC) computing, the coherent execution of algorithms on quantum and classical resources is a critical challenge. Most HQC algorithms involve iterative exchanges of data between quantum and classical processors, causing system bottlenecks and leading to high latency in applications. In this paper, we propose a novel framework that unifies quantum and reconfigurable resources for HQC algorithms, to mitigate system bottlenecks and latency. The proposed framework integrates Field-Programmable Gate Arrays (FPGAs) with quantum processing units (QPUs) for deploying HQC algorithms. Classical subroutines of the algorithms are accelerated on FPGA fabric using a high-throughput processing pipeline, while quantum subroutines are executed on QPUs. High-level software is used to seamlessly facilitate workload distribution and data exchange between classical and quantum processors. To evaluate the proposed framework, an HQC algorithm, namely variational quantum classification and MNIST dataset are used as a test case. The results demonstrate that the FPGA pipeline achieves up to8×improvement in runtime compared to the baseline of a state-of-the-art quantum software framework running on a server-grade CPU.
Introduction Hybrid Variational Quantum Algorithms (VQAs) present a highly viable pathway to near-term quantum utility; however, their performance is fundamentally bottlenecked by classical-quantum communication latency in Quantumas-a-Service (QaaS) environments. Methods This paper proposes an optimized classical-quantum orchestration architecture designed to minimize cloud-induced latency and maximize Quantum Processing Unit (QPU) active compute time. By implementing edge-colocated classical optimizers alongside batched parameter-shift gradient evaluations, the system circumvents stateless cloud API barriers. Results Benchmarking across parameterized quantum circuits ranging from 15 to 50 qubits demonstrates an 84% reduction in network-induced QPU idle time. The framework yields a 3.2 × speedup in overall convergence time for the Quantum Approximate Optimization Algorithm (QAOA) and up to a 98% reduction in classical API call overhead compared to standard RESTful QaaS execution models. Discussion These quantitative findings demonstrate that tightly coupled hybrid co-processing, physically adjacent to the control electronics, is critical for extending the computational bound of Noisy Intermediate-Scale Quantum (NISQ) devices.
Quantum computing is often treated as an experimental add-on: it is often loosely coupled to classical infrastructure through high-level interpreted languages, cloud-based orchestration and physical measurement hardware. However, future deployments in both high-performance computing (HPC) and embedded environments will demand tighter integration for lower latencies, stronger determinism, and architectural consistency. We propose a vertically integrated quantum systems architecture that treats quantum accelerators as peripheral system components. A central element is the Quantum Abstraction Layer (QAL), introduced at the kernel level of the operating system. This design enables real-time, low-latency, and high-throughput interaction between quantum and classical resources and opens the door for robust scheduling, resource management, and cross-stack optimisation. Kernel-space integration is not merely a technical curiosity—it is a necessity. For HPC, it enables scalable, heterogeneous workloads; for embedded systems, it provides a foundation for future quantum deployments far beyond scripting-based control interfaces. We present early-stage results including a virtual QPU model integrated into a QEMU-based prototype system. The architecture is validated through functional emulation and time-accurate FPGA simulations, enabling realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the groundwork for a system-level co-design methodology tailored for the next generation of quantum-classical computing.