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The European Physical Journal Plus

Noise resilience in symmetric exchange interactions on NISQ processors

M. AbuGhanem

Published May 19, 2026• 0 citations
Publisher
DOI
10.1140/epjp/s13360-026-07757-8

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The recent development of logical quantum processors marks a pivotal transition from the noisy intermediate-scale quantum (NISQ) era to the fault-tolerant quantum computing (FTQC) era. These devices have the potential to address classically challenging problems with polynomial computational time using quantum properties. However, they remain susceptible to noise, necessitating noise resilient algorithms. We introduce Quantum Zeno Monte Carlo (QZMC), a classical-quantum hybrid algorithm that demonstrates resilience to device noise and Trotter errors while showing polynomial computational cost for a gapped system. QZMC computes static and dynamic properties without requiring initial state overlap or variational parameters, offering reduced quantum circuit depth.
We report on a fundamental disparity between stochastic noise models and algorithmic performance in NISQ-era classifiers. Utilizing the ibm_kingston processor, we characterize the "Kingston Constant" (κ≈0.07κ\approx 0.07κ≈0.07), representing a 93% signal magnitude collapse. Despite this decay, we show via a hardware-calibrated stochastic digital twin that a Hadamard Test based Perceptron maintains a 93.9% accuracy for the MNIST dataset, validating our proposed Hadamard Resilience Effect under affine depolarization. Through parametric simulation, we establish a critical gate-noise threshold at λcrit≈0.65λ_{\text{crit}} \approx 0.65λcrit​≈0.65 (corresponding to a critical signal retention αcrit≈0.35α_{\text{crit}} \approx 0.35αcrit​≈0.35) where topological rank preservation breaks down. Furthermore, physical execution at high feature depths (N=256N = 256N=256) reveals a systemic divergence---the ``Coherence Gap'' (Δρ≈0.91Δρ\approx 0.91Δρ≈0.91)---where physical hardware classification accuracy collapses to 53.0\% due to a ``Coherence Wall'' at a circuit depth (D≈10kD \approx 10\text{k}D≈10k) exceeding the hardware's resilient depth limit (Dmax≈3.5kD_{\text{max}} \approx 3.5\text{k}Dmax​≈3.5k). This gap is consistent with coherent phase errors and crosstalk being the dominant unmodeled contributors under the tested hardware configuration, establishing a predictive operational boundary for NISQ classification architectures.