Quantum integrated sensing and communication (QISAC) is emerging as a key paradigm for next-generation quantum technologies, in which entanglement, coherence, and non-classical correlations are jointly exploited to enable secure communication, distributed sensing, and networked quantum functionalities. As quantum systems transition from laboratory demonstrations to deployable infrastructures, performance is increasingly limited not by individual components but by cross-layer interactions among hardware noise, channel loss, error-management strategies, and network architecture. This survey presents a system-level architectural framework for QISAC, focusing on how physical-layer constraints, quantum channel characteristics, and error-mitigation mechanisms jointly determine end-to-end performance and architectural feasibility in scalable quantum networks. We analyze representative quantum hardware platforms-including superconducting circuits, trapped ions, neutral atoms, photonic systems, and solid-state spin qubits-through the lens of coherence time, fidelity, interface capability, and technology readiness, emphasizing their implications for networked sensing and communication rather than device-level operation. The roles of quantum error correction (QEC) and entanglement purification are examined as complementary error-management layers, highlighting trade-offs among resource overhead, latency, and achievable entanglement fidelity under realistic noise and memory constraints. We further connect these architectural considerations to QISAC-enabled applications such as distributed quantum sensing, quantum key distribution (QKD), and repeater-assisted entanglement distribution, clarifying how hardware limitations and error-management choices propagate to application-level performance. By synthesizing noise, error management, and network co-design into a unified system perspective, this survey provides design-oriented insights and architectural guidelines for building scalable, noise-resilient QISAC networks.
Quantum integrated sensing and communication (QISAC) is emerging as a key paradigm for next-generation quantum technologies, in which entanglement, coherence, and non-classical correlations are jointly exploited to enable secure communication, distributed sensing, and networked quantum functionalities. As quantum systems transition from laboratory demonstrations to deployable infrastructures, performance is increasingly limited not by individual components but by cross-layer interactions among hardware noise, channel loss, error-management strategies, and network architecture. This survey presents a system-level architectural framework for QISAC, focusing on how physical-layer constraints, quantum channel characteristics, and error-mitigation mechanisms jointly determine end-to-end performance and architectural feasibility in scalable quantum networks. We analyze representative quantum hardware platforms-including superconducting circuits, trapped ions, neutral atoms, photonic systems, and solid-state spin qubits-through the lens of coherence time, fidelity, interface capability, and technology readiness, emphasizing their implications for networked sensing and communication rather than device-level operation. The roles of quantum error correction (QEC) and entanglement purification are examined as complementary error-management layers, highlighting trade-offs among resource overhead, latency, and achievable entanglement fidelity under realistic noise and memory constraints. We further connect these architectural considerations to QISAC-enabled applications such as distributed quantum sensing, quantum key distribution (QKD), and repeater-assisted entanglement distribution, clarifying how hardware limitations and error-management choices propagate to application-level performance. By synthesizing noise, error management, and network co-design into a unified system perspective, this survey provides design-oriented insights and architectural guidelines for building scalable, noise-resilient QISAC networks.
Quantum communication and information technologies are poised to transform secure data transmission, distributed quantum computing, and scalable networking by leveraging fundamental principles such as superposition, entanglement, and the no-cloning theorem. This survey presents a structured overview of the quantum information processing (QIP) landscape, spanning theoretical foundations to system-level architectures. We cover quantum states, unitary evolution, gates, and channels, leading to the mathematical framework of quantum operations and the effects of decoherence. Quantum error correction (QEC) is examined through block codes and fault-tolerant operations, along with its integration with entanglement purification to address challenges of noisy intermediate-scale quantum (NISQ) devices. Physical platforms, including gate-based, continuousvariable and measurement-based models, are analyzed with an emphasis on error mitigation strategies to preserve coherence. We also discuss advancements in quantum sensing, particularly phase estimation, and evaluate communication protocols such as quantum key distribution (QKD) and teleportation in terms of fidelity, efficiency, and resilience. At the system level, components such as quantum networks, repeaters, and routers are reviewed with attention to scalability and security. Each section concludes with lessons learned, reflecting on challenges, trade-offs, and open questions. The survey culminates in outlining future directions in hybrid QEC-sensing integration, AI-enhanced error correction, and topological architectures, offering a forward-looking perspective on the co-evolution of quantum technologies. By bridging theory, protocols, physical systems, and architectures, this work charts a comprehensive roadmap toward secure, scalable, and high-fidelity quantum communication.
This survey examines quantum error correction (QEC) as a cross-layer engineering problem for scalable fault-tolerant quantum computing and protected quantum communication. It covers code and noise models, hardware platforms and physical-integration constraints, real-time decoding and control, system-scale resource limits, and QEC for quantum communication. Across these areas, the survey uses a three-stage analytical lens consisting of physical realizability, real-time executability, and system-scale or end-to-end utility, together with common criteria including logical reliability, timing and throughput, quantum and classical resource overhead, connectivity and data movement, physical-integration and power constraints, and communication rate and fidelity. Overall, the survey shows that scalable QEC depends on coordinated advances across codes, devices, control, decoding, architecture, and communication.
The pursuit of a universal, fault-tolerant quantum computer has transformed quantum computing from a predominantly theoretical discipline into a rapidly diversifying hardware ecosystem. This review presents a comprehensive and technically grounded analysis of the principal physical qubit modalities: superconducting circuits, trapped ions, photonic platforms, neutral atoms, semiconductor spin qubits, and topological approaches, focusing on their underlying operating principles, performance characteristics, and system-level constraints. We examine how these qubit technologies are embedded within scalable quantum processor architectures, including control and readout infrastructures, connectivity topologies, and quantum error correction strategies. The review provides a comparative study of key performance metrics, such as coherence times, gate fidelities, error rates, and scalability, reveals fundamental trade-offs between speed, robustness, and operational complexity that shape distinct technological roadmaps and target applications. We further highlight the ongoing transition from noisy intermediate-scale quantum (NISQ) devices toward architectures centred on logical qubits, driven by advances in materials engineering, precision control, and quantum information theory. Together, these developments sketch the emerging routes toward fault-tolerant quantum computing and practical quantum advantage, while offering readers a coherent entry point and reference guide to the current quantum hardware landscape.
This review synthesizes current understanding of decoherence pathways across leading hardware platforms and explains why several experimentally observed noise features—drift, burst events, coherent components, correlated and non-Markovian structure, and leakage—can be disproportionately damaging for QEC. Decoherence remains the dominant impediment to scalable quantum computing because it is not a single error mechanism but a system-level phenomenon arising from materials defects, electromagnetic loss, control electronics, measurement backaction, and the broader environment in which a processor operates. Quantum error correction (QEC) is designed to algorithmically suppress physical noise, yet its practical success depends on how closely real devices satisfy the assumptions under which fault tolerance is proved: approximate locality, weak temporal correlations, sufficiently stochastic error statistics, low leakage, and reliable syndrome extraction. We then evaluate fundamental and engineering challenges that shape the viability of QEC at scale: syndrome measurement fidelity, correlated error suppression, decoding latency and classical co-processing, architectural constraints (connectivity, crosstalk, calibration overhead), and the resource cost of implementing a universal fault-tolerant gate set. Recent demonstrations of below-threshold behaviour and “break-even” regimes show that QEC is transitioning from theory to practice, but also clarify what remains unresolved: maintaining stable noise below fault-tolerance targets over long times, scaling to many logical qubits with low correlated-error rates, and integrating hardware-aware codes and decoders. We conclude with research priorities that treat decoherence and QEC as part of a co-designed stack spanning device physics, control, architecture, and algorithms.
Quantum Key Distribution (QKD) has progressed from a theoretical cryptographic concept to an emerging secure communication infrastructure technology. While early work focused on protocol security and physical-layer feasibility, current research increasingly addresses scalable network deployment, hardware acceleration, and integration with classical communication systems. As QKD expands from point-to-point links to metropolitan, backbone, and hybrid satellite–terrestrial networks, new engineering challenges arise in topology design, entropy generation, real-time key distillation, and multi-vendor interoperability. This survey provides an infrastructure-oriented review of QKD networks, examining architectural models, quantum randomness as a root of trust, FPGA and system-on-chip (SoC) based acceleration techniques, and programmable control-plane integration. Key management system architectures and standardized interfaces are analyzed to highlight their roles in enabling scalable, interoperable deployments. The paper also synthesizes major standardization efforts and deployment initiatives shaping carrier-grade QKD infrastructures. Finally, open engineering challenges, including scalability, control-plane integration, certification harmonization, and hybridization with post-quantum cryptography, are identified, positioning QKD as a foundational component of next-generation secure communication systems.
The rapid evolution of communication networks, driven by the expansion of heterogeneous environments such as 6G, Internet of Things (IoT), and edge computing, has exposed a critical research gap in the lack of unified frameworks that jointly address intelligent network control and quantum-resilient security. Existing networking protocols were originally designed under static configurations and classical security assumptions, making them increasingly inadequate for dynamic, large-scale, and intelligent infrastructures exposed to quantum-enabled threats. At the same time, the emergence of Quantum Computing (QC) introduces severe security risks, as widely used cryptographic mechanisms supporting protocols such as Transport Layer Security (TLS) and Internet Protocol Security (IPsec) become vulnerable to quantum attacks. This paper presents a structured survey based on a systematic classification of recent literature across AI-enabled networking, Post-Quantum Cryptography (PQC), Quantum Key Distribution (QKD), and protocol-level integration approaches. The review categorizes existing works into AI-driven network optimization, quantum-resilient security mechanisms, and hybrid AI–QRC architectural frameworks, enabling a unified comparison of design strategies and deployment models. Furthermore, this survey analyzes how Artificial Intelligence (AI) techniques enable autonomous network operations while Quantum-Resilient Cryptography (QRC) approaches provide post-quantum security guarantees, highlighting their complementary roles in next-generation network design. The study further synthesizes key findings for a tightly coupled AI–QRC co-design, which remains an open challenge due to mismatched assumptions in control latency, cryptographic overhead, and protocol adaptability. Additionally, this review emphasizes the need for integrated frameworks that combine intelligence and quantum security to develop adaptive, scalable, and resilient network protocols for the post-quantum era.