Modern quantum error-correction pipelines are increasingly assembled from heterogeneouscomponents: neural predecoders trained on stabilizer syndromes, heuristic local correctors,and symbolic exact routines. Each component is correct in its regime and wrong outsideit, and a deployment decision must be made per workload, per round, under real-timeconstraints. We present a reproducible trust-layer and routing demonstrator for NVIDIA-style Ising-family surface-code predecoders, packaged as a standalone public artifact. Thesystem combines four load-bearing ingredients: (i) a hash-pinned benchmark surface of512 dual-basis distance-13 samples with SHA-256 contracts on every committed artifact;(ii) a provenance-forensics layer that executably localizes replay mismatches to the specificpipeline stage responsible for them; (iii) a structured-regime routing policy derived froma signed benchmark delta rather than a hand-tuned threshold, with a falsifiable mutationtest that proves the lane selection follows the evidence and not the implementer; and (iv) aCUDA-Q preflight that reports deployment readiness honestly, distinguishing “importable”from “realtime-ready.” We report exact historical parity: 512/512 matching samples acrossboth X and Z stabilizer bases, with the heuristic lane and the NVIDIA-lane outputs agreeingsample-by-sample with the committed reference. On the 512-sample benchmark the NVIDIAlane lifts mean resolved fraction by ∆ = +0.638 on line-propagation regimes and ∆ = +0.595on cycle-event regimes, while incurring ∆ = −0.080 on local-noise regimes — supportinga three-lane routing rule that the infrastructure encodes and tests. The complete artifact,including Lean-compatible reproducibility contracts and a patch-ready CUDA-Q executionpath, is published at https://github.com/Abraxas1010/ising-trust-routing.
Modern quantum error-correction pipelines are increasingly assembled from heterogeneouscomponents: neural predecoders trained on stabilizer syndromes, heuristic local correctors,and symbolic exact routines. Each component is correct in its regime and wrong outsideit, and a deployment decision must be made per workload, per round, under real-timeconstraints. We present a reproducible trust-layer and routing demonstrator for NVIDIA-style Ising-family surface-code predecoders, packaged as a standalone public artifact. Thesystem combines four load-bearing ingredients: (i) a hash-pinned benchmark surface of512 dual-basis distance-13 samples with SHA-256 contracts on every committed artifact;(ii) a provenance-forensics layer that executably localizes replay mismatches to the specificpipeline stage responsible for them; (iii) a structured-regime routing policy derived froma signed benchmark delta rather than a hand-tuned threshold, with a falsifiable mutationtest that proves the lane selection follows the evidence and not the implementer; and (iv) aCUDA-Q preflight that reports deployment readiness honestly, distinguishing “importable”from “realtime-ready.” We report exact historical parity: 512/512 matching samples acrossboth X and Z stabilizer bases, with the heuristic lane and the NVIDIA-lane outputs agreeingsample-by-sample with the committed reference. On the 512-sample benchmark the NVIDIAlane lifts mean resolved fraction by ∆ = +0.638 on line-propagation regimes and ∆ = +0.595on cycle-event regimes, while incurring ∆ = −0.080 on local-noise regimes — supportinga three-lane routing rule that the infrastructure encodes and tests. The complete artifact,including Lean-compatible reproducibility contracts and a patch-ready CUDA-Q executionpath, is published at https://github.com/Abraxas1010/ising-trust-routing.
Quantum error-correction decoders are typically benchmarked against synthetic circuit-level noise, under the assumption that a decoder's ranking under such noise transfers to hardware and improves as the noise model becomes more realistic. The Willow processor, the first to operate below the surface-code threshold, allows us to test this assumption. We rank a panel of six decoders using a four-rung ladder of noise models with increasing fidelity, evaluated against real data across three code distances, two bases, and fifteen round counts. Rank agreement with hardware appears once the noise model gives each operation type its own error rate. Calibrating the model to the device improves absolute error rates but not rank agreement. We additionally provide the first independent evaluation of NVIDIA's Ising pre-decoder on hardware, at code distances below its training receptive field and via a mapping onto the lattice on which it was trained. Under these conditions, it holds no accuracy-latency advantage: another panel decoder matches or improves on it in both per-cycle error rate and decode latency in 278 of the 280 evaluations. We release the full pipeline and the per-shot outcome of every evaluation, so future decoders and devices can be compared.
QECTOR Decoder Benchmark Datasets & Empirical Reports This repository hosts the evolving collection of reproducible benchmark datasets, JSON measurement artifacts, and empirical performance reports for the QECTOR Decoder v3 platform (Rust/Python quantum error-correction decoder). Each versioned deposit contains environment-stamped, content-hashed JSON artifacts together with the corresponding publication-grade report. All numerical results are fully regenerable from the published wheels and the scripts listed in the reproducibility sections. Scope across versions Code-capacity and circuit-level (Stim rotated_memory_z) evaluations Throughput (shots/s, measure-s/shot), logical error rates with 95 % Wilson intervals, syndrome faithfulness (GF(2) exact check), and CUDA-vs-CPU bit identity Decoder families: FastUnionFind, UnionFind, Blossom (exact MWPM), SparseBlossom, Batch/CPUBatch, BPOSD, HybridCascade, AmbiguityCluster, LookupTable, and CUDABatch (unweighted + DEM-weighted) Hardware provenance, licence-tier disclosure (GPU gated behind Enterprise), and SHA-256 inventories of every backing artifact Version history (selected) v0.6.6 (July 2026) – Workbench Benchmark Master Report: 1 858 decode-timing measurements from 105 runs, six code topologies (Heavy Hex, Repetition, Ring, Rotated Surface, Toric, Unrotated Surface), fixed p = 0.05, distances d = 3–19. Focus on raw latency, harmonic-mean throughput and peak memory. v0.6.8 - Empirical edge-hardware benchmarks. v0.7.0 (August 2026) – Full Empirical Decoder Benchmark Report on the published wheel: nine CPU families + CUDA batch path, circuit-level LER parity with PyMatching 2.4.0, exact syndrome faithfulness, DEM-weighted GPU scaling restoration, and complete artifact inventory (Appendix A). All figures and tables in the accompanying reports are regenerated from the JSON files listed with their SHA-256 hashes; no pre-release numbers are carried forward. Related resources PyPI: qector-decoder-v3 Repository: https://github.com/GuillaumeLessard/qector-decoder Website: https://www.qector.store
Fault-tolerant quantum computing with the surface code requires a classical decoder that returns a correction in less than one syndrome extraction round-a latency budget of approximately 1 us on superconducting hardware that is below what software decoders achieve and at the edge of what FPGA and GPU implementations report. We present tt-qec-predecoder, an end-to-end pre-decoder system targeting this regime by mapping a selective-scan state-space model (Mamba/S6) onto the Tenstorrent Blackhole RISC-V tensor architecture, combined with a hardware-resident integrity and formal-verification pipeline. The decoder is a 16 M-parameter Sparse Mamba network whose recurrence has O(k) work in k, the number of non-trivial syndrome bits, executed as a tile-resident Tensix kernel with no host round-trip. Around the kernel we build a Z3-based proof framework that discharges five abstract safety obligations (no NoC deadlock, no buffer overflow, worst-case latency bound, fixed-point quantizer error bound, no-op safety), a BLAKE3 content-addressed integrity chain (QCIVET) covering every artifact from training data to deployed weights, and a standardized benchmarking suite (qec-lego-bench) for like-for-like comparison against PyMatching (CPU), Micro Blossom (FPGA), and NVIDIA Ising (GPU) baselines at code distances d = {3,5,7,9, 13, 17, 21, 25, 32}. We describe the architecture, the kernel design and its hardware-aware Taylor-approximated discretization, the verification methodology and its current limitations, and the benchmarking framework. We additionally report a first round of experimental validation: measured CPU baselines on the FP32 dense reference model, Blackhole latencies projected from those baselines through a published scaling chain (INT4 quantization, tensor-core SIMD, Tenstorrent NoC streaming), an end-to-end decode run on the IBM Quantum cloud simulator, and as a new empirical result-50,000 shots of raw complex-valued IQ syndrome data harvested from a real IBM Heron R2 processor (ibm_fez) via the IBM Quantum open plan. Real-hardware Blackhole validation remains explicitly pending.
Fast, scalable decoding architectures that operate in a block-wise parallel fashion across space and time are essential for real-time fault-tolerant quantum computing. We introduce a scalable AI-based pre-decoder for the surface code that performs local, parallel error correction with low decoding runtimes, removing the majority of physical errors before passing residual syndromes to a downstream global decoder. This modular architecture is backend-agnostic and composes with arbitrary global decoding algorithms designed for surface codes, and our implementation is completely open source. Integrated with uncorrelated PyMatching, the pipeline achieves end-to-end decoding runtimes of order O(1μs) per round at large code distances on NVIDIA GB300 GPUs while reducing logical error rates (LERs) relative to global decoding alone. In a block-wise parallel decoding scheme with access to multiple GPUs, the decoding runtime can be reduced to well below O(1μs) per round. We observe further LER improvements by training a larger model, outperforming correlated PyMatching up to distance-13. We additionally introduce a noise-learning architecture that infers decoding weights directly from experimentally accessible syndrome statistics without requiring an explicit circuit-level noise model. We show that purely data-driven graph weight estimation can nearly match uncorrelated PyMatching and exceed correlated PyMatching in certain regimes, enabling highly-optimized decoding when hardware noise models are unknown or time-varying, as well as training pre-decoders with realistic noise models. Together, these results establish a practical, modular, and high-throughput decoding framework suitable for large-distance surface-code implementations.
Real-time decoding is a major bottleneck in scaling quantum error correction (QEC) from noisy intermediate-scale quantum (NISQ) devices to fault-tolerant quantum computing. We present an adaptive confidence-gated decoding framework for the rotated surface code that treats decoding as a two-stage inference problem. A lightweight feed-forward neural network performs fast-path decoding for the majority of syndrome measurements, while only low-confidence predictions are escalated to a minimum-weight perfect matching (MWPM) refinement stage. We benchmark the framework on rotated surface codes with distances d∈{3,5,7,9,11} under circuit-level depolarising noise using the Stim stabiliser simulator. The evaluation characterises logical accuracy, confidence-controlled accuracy-latency trade-offs, decoding throughput, per-shot latency, and decoding-graph resource scaling. Routing only 3.3%-6.2% of syndromes to the refinement stage improves logical accuracy from 99.21% for the neural-only baseline to 99.81% at a confidence threshold of 0.95 while incurring only a bounded increase in average decoding cost. Neural-decoder throughput saturates near 4.6×105 samples s−1 at batch size 512 on commodity CPU hardware, indicating that the neural fast path is not the dominant throughput bottleneck beyond code distance d=7. We release the complete benchmarking pipeline, trained models, raw benchmark data, and source code, and explicitly distinguish the experimentally validated contributions from the broader hardware-aware QEC co-design roadmap, including hardware-constrained code discovery, GPU-accelerated inference, and multi-noise optimisation, which remain directions for future work.
This manuscript specifies a mid-level, standards-ready controller for networked quantum sensing under a Four-Solves-Three (4S3) contract. Four fixed roles (D, A, B, C) decide three gates—parity hygiene, centered-network co-lock, and corridor severity—without threshold travel and with tokens-only replay. The physical setting is a compact continuous-variable network that enables weighted-sum estimation on the determinant lane (D). I/Q centering (L1/L2) anchors the estimator; z_tension operates as a stop-token budget. Device-independent falsifiers (flip-only phase, disable-L, withhold-node, leave-one-out) are executed at network scale. Heisenberg claims are bound-respecting via a preregistered Fisher ratio band and an identifiability angle token. Two guard-safe routes are contrasted under the same contract: Route A (Magnon Electric Readout, direct D-lane weighted sum) and Route B (Angular Ribbon Mid-Stream Tap, advisory-only centering/stop). A minimal replication kit (frozen graph/weights/mask, detector model, and JSON schemas) allows third parties to reproduce IoU and rho, rerun falsifiers, and verify acceptance from tokens alone.