Significant — This article, Logical Error Attribution to Sign-First Custody: Typed-Zero Control for Dual-Rail Superconducting Qubits, uses a significant and serious dual-rail erasure-qubit hardware result as the occasion to unify a sign-first chain built from Contain And Continue, Randomness, Rethinking Noise, Sign Net Detour, and Fingerprints in 3D. The paper argues that the key missing object is not another late logical-pathology story but a smaller post-gate control row written as committed sign, front-end 0T, or back-end 0S under frozen recognition, fixed enforcement, stored-anchor custody, and no-backflow. It then shows how bounded detour work in Richardson Subspace, typed-zero accounting, 3D protection, and QCore’s corridor-first horizon together provide a more portable and contract-grade answer than late diagnostic narration alone.
Significant — This article, Logical Error Attribution to Sign-First Custody: Typed-Zero Control for Dual-Rail Superconducting Qubits, uses a significant and serious dual-rail erasure-qubit hardware result as the occasion to unify a sign-first chain built from Contain And Continue, Randomness, Rethinking Noise, Sign Net Detour, and Fingerprints in 3D. The paper argues that the key missing object is not another late logical-pathology story but a smaller post-gate control row written as committed sign, front-end 0T, or back-end 0S under frozen recognition, fixed enforcement, stored-anchor custody, and no-backflow. It then shows how bounded detour work in Richardson Subspace, typed-zero accounting, 3D protection, and QCore’s corridor-first horizon together provide a more portable and contract-grade answer than late diagnostic narration alone.
Foundational — Gate-On First: A Bidirectional Sign-Net Protocol for Controlled-Z Gate Certification with Typed-Zero, Mapped Support Matching, and D4 Custody. This article should be read as a reusable external-certification architecture for connecting device-independent quantum-gate evidence to Sign-Net decision custody. The protocol records the gate-on block first as a frozen, ungraded candidate while preserving the source-compatible certification order in which the identity-setting correlations establish the upstream reference structure before the unitary-setting evidence receives authority. Full device-independent and almost device-independent operation remain separate report classes, and the Sign-Net engine receives only committed external settings, outcomes, source and repeater records, isolation evidence, confidence intervals, and frozen reference definitions rather than hidden information from inside the tested gate. The article replaces literal Local-inside-Universal language with mapped support matching across distinct observations. A Local record containing four mapped items and a gate-on record containing ten items can establish four shared matches and six active-only items without treating the two physical conditions as simultaneously nested. A two-knob measurement then reads bottom-up Local somethingness represented in the gate-on candidate and top-down gate-on nothingness relative to the Local demand. These quantities use separate denominators and remain distinct from physical emptiness, unresolved missingness, (0T), and inherited (0S) custody. Cross-Chain Closure compares the opposed Local/identity records at the fixed (S=0) address and separately compares the returned gate-on block with the frozen first observation. D4 retains candidate evaluation, typed-zero review, mapped matching, final grading, and all onward promotion authority. D5 provides bounded recovery and Strong-to-Weak witness return, while D6 receives only D4-authored full-sign or Strong-to-Weak (0S) promotion. A fourteen-scenario Monte Carlo grammar test produces fifteen thousand baseline D6 promotions with zero false-physical certifications, zero unsafe promotions, and zero missed-certifiable outcomes inside the declared synthetic suite. A separate Weaker-to-D6 countertest produces five thousand false and unsafe promotions, directly fixing the promotion boundary while leaving Bell self-testing and physical device-independent implementation to upstream experimental work.
Foundational — QCore 6: Pre-Binary Sign Net Worker Beyond Quantum A-to-B, With SCADA Release — This article presents QCore 6 as the successor architecture to QCore V, preserving the pre-binary local worker while adding Sign Net custody, SCADA release, read-through M witness measurement, Sadovskii Spin First, upstream lattice carry, double-detour return, and endpoint verification into one runtime order. The central claim is that QCore remains outside the native Quantum A-to-B corridor: A-to-B, Bob verification, midpoint witness drains, binary handling, and SCADA command flow become client or bridge uses of a worker result rather than the original storytelling layer. QCore 6 classifies the richer object before ordinary binary, public-row, command-client, or endpoint authority becomes live. The worker freezes the run, declares custody, preserves typed-zero pressure, separates recognition from enforcement through SEB and MAP, releases only bounded survivors, and verifies exported endpoints through sealed capsules. The article also supplies a JSON-style replay template and falsifiable tests for SCADA custody, stored-anchor separation, 2.75 continuity, Sadovskii Spin First, lattice forecast, read-only M witness use, double-detour return, and full QCore 6 replay.
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computation. To this end, we introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace, [Formula: see text], of two superconducting microwave cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are in general much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers unique capabilities. Using just one additional transmon ancilla per dual-rail qubit, we describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors in the cavities and the transmon can be detected and converted to erasure errors in all operations, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit exhibits a favorable hierarchy of error rates and is expected to perform well below the relevant QEC thresholds with today's coherence times.
Qubits that experience predominantly erasure errors offer distinct advantages for fault-tolerant operation. Indeed, dual-rail encoded erasure qubits in superconducting cavities and transmons have demonstrated high-fidelity operations by converting physical-qubit relaxation into logical-qubit erasures, but this comes at the cost of increased hardware overhead and circuit complexity. Here, we address these limitations by realizing erasure conversion in a single fluxonium operated at zero flux, where the logical state is encoded in its 0-2 subspace. A single, carefully engineered resonator provides both mid-circuit erasure detection and end-of-line (EOL) logical measurement. Post-selection on non-erasure outcomes results in more than four-fold increase of the logical lifetime, from 193μs to 869μs. Finally, we characterize measurement-induced logical dephasing as a function of measurement power and frequency, and infer that each erasure check contributes a negligible error of 7.2×10−5. These results establish integer-fluxonium as a promising, resource-efficient platform for erasure-based error mitigation, without requiring additional hardware.
Erasure qubits -- qubits designed to have an error profile that is dominated by detectable leakage errors -- are a promising way to cut down the resources needed for quantum error correction. There have been several recent experiments demonstrating erasure qubits in superconducting quantum processors, most notably the dual-rail qubit defined by the one-photon subspace of two coupled cavities. An outstanding challenge is that the ancillary transmons needed to facilitate erasure checks and two-qubit gates introduce a substantial amount of noise, limiting the benefits of working with erasure-biased qubits. Here, we show how to suppress the adverse effects of transmon-induced noise while performing erasure checks or two-qubit gates. We present control schemes for these operations that suppress erasure check errors by three orders of magnitude and reduce the logical two-qubit gate infidelities by up to three orders of magnitude.
Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.