Near-term quantum processors operate in a regime fundamentally constrained by environ-mental noise. Current quantum devices experience substantial fidelity degradation from threeprimary noise channels—amplitude damping, phase damping, and depolarizing noise—whichscale catastrophically with circuit depth. Traditional quantum error correction frameworksimpose prohibitive logical-to-physical qubit overhead ratios, rendering them infeasible fornear-term quantum devices. A critical gap exists between raw hardware capabilities andfault-tolerant quantum computation. Addressing this gap requires practical methodologies that enhance circuit resilience with-out requiring hardware restructuring or deep error correction implementations. This researchintroduces TOPAZ (Topology OPtimization Ansatze with Zoning), a topology-preservingoptimization framework that systematically enhances quantum circuit resilience throughstrategic parameter tuning. Unlike structural redesign approaches, TOPAZ maintains cir-cuit connectivity unchanged, enabling passive enhancement that serves as a baseline forcomplementary error mitigation techniques. The novelty of TOPAZ encompasses three principal dimensions. First, it combines theParametric Trotter Expression (PTE) framework with specialized adaptation of the Method of Moving Asymptotes (MMA)—a classical optimization technique proven effective in struc-tural topology optimization—to the quantum parameter space. Second, it implements real-istic, spatially-correlated noise modeling across three independent channels, replacing sim-plified uncorrelated noise assumptions. Third, it demonstrates that passive parameter op-timization yields multiplicative fidelity improvements when combined with techniques likevirtual distillation. This paper presents the complete TOPAZ framework, detailing its mathematical founda-tions, algorithmic implementation, and experimental validation across multi-qubit systemsunder authentic NISQ noise conditions.
Near-term quantum processors operate in a regime fundamentally constrained by environ-mental noise. Current quantum devices experience substantial fidelity degradation from threeprimary noise channels—amplitude damping, phase damping, and depolarizing noise—whichscale catastrophically with circuit depth. Traditional quantum error correction frameworksimpose prohibitive logical-to-physical qubit overhead ratios, rendering them infeasible fornear-term quantum devices. A critical gap exists between raw hardware capabilities andfault-tolerant quantum computation. Addressing this gap requires practical methodologies that enhance circuit resilience with-out requiring hardware restructuring or deep error correction implementations. This researchintroduces TOPAZ (Topology OPtimization Ansatze with Zoning), a topology-preservingoptimization framework that systematically enhances quantum circuit resilience throughstrategic parameter tuning. Unlike structural redesign approaches, TOPAZ maintains cir-cuit connectivity unchanged, enabling passive enhancement that serves as a baseline forcomplementary error mitigation techniques. The novelty of TOPAZ encompasses three principal dimensions. First, it combines theParametric Trotter Expression (PTE) framework with specialized adaptation of the Method of Moving Asymptotes (MMA)—a classical optimization technique proven effective in struc-tural topology optimization—to the quantum parameter space. Second, it implements real-istic, spatially-correlated noise modeling across three independent channels, replacing sim-plified uncorrelated noise assumptions. Third, it demonstrates that passive parameter op-timization yields multiplicative fidelity improvements when combined with techniques likevirtual distillation. This paper presents the complete TOPAZ framework, detailing its mathematical founda-tions, algorithmic implementation, and experimental validation across multi-qubit systemsunder authentic NISQ noise conditions.
This repository contains the framework, data, and methodology for TOPAZ v2 (Topology OPtimization Ansatze with Zoning). TOPAZ is a high-performance research framework that introduces Quantum Topology Optimization as a proactive layer for designing noise-resilient quantum circuits. While conventional quantum error mitigation (QEM) operates post-execution on measurements, TOPAZ v2 enables intrinsic resilience by tuning the circuit’s physical parameters—specifically Intensity (ρ) and Timing (τ)—to navigate the parameter manifold toward regions of inherent robustness.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Abstract Quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices require optimization strategies matched to circuit structure. We present two complementary approaches: VERMICULAR, achieving 93.0% success rates for Grover’s algorithm through strategic dynamical decoupling (DD) placement (vs. 18.3% baseline), and systematic QAOA parameter optimization achieving 94.5% approximation ratios for MaxCut (vs. 39.6% with theoretical parameters). Through >15,000 circuit executions across IQM Garnet, Rigetti Ankaa-3, and IonQ Forte-1 (total cost: €70), we demonstrate that circuit structure determines which strategy succeeds: DD helps algorithms with substantial idle time (Grover: 34% idle → 5× improvement) but degrades continuously-active circuits (QAOA: 2.4% idle → 50% degradation with DD). We systematically characterize algorithm noise resilience via critical noise thresholds (σc), finding Bell states achieve 4× higher σc than product states (0.200 vs 0.050, p < 0.001) and that σc predicts hardware performance (r = 0.94, p = 0.006). QAOA scaling studies (3-40 qubits) reveal exponential decay with 56% plateau beyond 20 qubits. Simulator-optimized parameters transfer effectively to hardware (85-98% efficiency), but hardware-to-hardware transfer requires architecture-specific tuning. We provide SigmaCSuite, an open-source validation framework, and complete experimental protocols. These findings establish that optimization strategy must match circuit structure: idle-time protection for search algorithms, parameter tuning for variational algorithms—achieving 2.5-5× improvements through targeted approaches.
Variational quantum circuits (VQCs) solving partial differential equations (PDEs) on near-term quantum hardware face a critical challenge: hardware noise degrades solution fidelity and disrupts convergence. We present a systematic study of three noise channels; depolarizing, amplitude damping, and bit-flip on VQCs constrained by PDE residual loss functions for the heat equation, Burgers' equation, and the Saint-Venant shallow water equations. We benchmark three error mitigation strategies: zero-noise extrapolation (ZNE) via Richardson polynomial fitting, probabilistic error cancellation (PEC), and measurement error mitigation through inverse confusion matrices. Our numerical experiments on 6-qubit, 4-layer circuits demonstrate that ZNE reduces absolute error by 82-96% at low noise (p = 0.001), with effectiveness degrading gracefully at higher noise strengths. We prove analytically and confirm numerically that physics-constrained circuits exhibit inherent noise resilience: at p = 0.01, constrained circuits maintain 25-47% higher fidelity than unconstrained counterparts, with the advantage scaling with PDE complexity. PEC provides near-exact correction at low gate counts but incurs exponential sampling overhead, rendering it impractical beyond ~60 gates at p >= 0.02. Error budget decomposition reveals that systematic errors dominate at all noise levels (43-58%), while the PDE residual component grows from ~10% to ~31% as noise increases, indicating that physics constraints absorb noise through structured gradient information. These results establish practical guidelines for deploying variational PDE solvers on NISQ hardware.
The Quantum Approximate Optimization Algorithm (QAOA) is widely regarded as a promising near-term quantum algorithm for addressing hard combinatorial optimization problems on Noisy Intermediate-Scale Quantum (NISQ) devices; however, its real-world effectiveness is severely constrained by hardware noise, including gate infidelities, decoherence, and measurement errors. This work explores an error mitigation–driven approach to enhance the performance and robustness of QAOA without altering its algorithmic structure or requiring fault-tolerant quantum resources. Measurement error mitigation and zero-noise extrapolation are incorporated into the execution and post-processing stages of QAOA circuits and evaluated using the Minimum Vertex Cover problem as a representative benchmark. Performance is assessed through approximation ratios, solution stability, and noise sensitivity across multiple circuit depths. The results indicate that error mitigation not only improves approximation accuracy but also stabilizes output distributions and delays performance degradation at increased circuit depths. Additionally, the mitigated executions demonstrate better consistency across repeated runs, highlighting improved resilience to stochastic noise. These findings emphasize that lightweight and hardware-efficient error mitigation techniques can significantly extend the practical usability of QAOA on current NISQ hardware, providing a scalable and realistic pathway for executing quantum optimization algorithms more reliably in near-term quantum computing environments.
Abstract Noisy Intermediate-Scale Quantum (NISQ) devices are near-term quantum computing devices that inherently suffer from imperfect gate implementation, decoherence, and measurement noise. The main type of variational quantum algorithms(VQAs) is based on Parameterized Quantum Circuits (PQCs), which, however, face practical challenges due to optimization instability of optimization caused by noise and reduced performance. In this paper, we suggest a comprehensive noise-resilient optimization framework for PQCs, which explicitly incorporates noise-resilient circuit architecture design, incorporating noise-aware training strategies into the variational optimization loop. The framework uses circuit structures that are efficient in depth and are hardware compatible in addition to adaptive optimizer choice, stochastic optimization, and averaging as a part of repeated measurement to reduce the impacts of realistic noise. Large-scale experiments are performed with different amounts of qubits, depths of the circuit and noise strengths with realistic noise models. The findings indicate that the convergence rate is faster, the stability is increased, the variability of run-to-run variability is minimized, and other robustness is better than the noise-unaware optimization techniques. Moreover, systematic studies determine optimal operating regions that optimally trade-off expressibility and noise tolerance to offer useful design advice on trusted implementation of VQAs with near-term quantum hardware.