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Towards Scalable, Fault-Tolerant Quantum Computers: Multi-Logical-Qubit Architectures and Error Correction Advances

Azizi Othman

Published Jan 1, 2024• 0 citations
Publisher
DOI
10.13140/rg.2.2.23513.38245

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Fault-tolerant quantum computing requires not only reliable logical qubit storage, but also the ability to perform high-fidelity logical operations between error-corrected qubits at scale. While much of the existing literature focuses on optimizing syndrome extraction for a single logical qubit, the co-design of physical architectures that support both robust error correction and efficient logical computation remains an open challenge. In this work, we propose a multi-qubit spin-qubit shuttling bus architecture that addresses both requirements simultaneously. The architecture optimizes the physical qubit layout for syndrome extraction and supports transversal two-qubit logical gates between an arbitrary number of logical qubits, achieving all-to-all logical connectivity through coherent spin shuttling. We further propose an ancilla-sharing scheme that encodes multiple logical qubits within a single logical element, compressing the physical footprint of the processor and improving long-range gate fidelity. Extending the architecture from a one-dimensional bus to a two-dimensional grid of shuttling tracks reduces the inter-qubit distance, yielding consistent improvements in logical error. Finally, we apply the Quantum Reverse Mapping methodology at the logical level to optimize the layout of a \textit{15-to-1} magic state distillation circuit, demonstrating how the transversal capabilities of the proposed architecture can be leveraged for universal fault-tolerant computation. Taken together, these results establish a principled co-design framework that bridges the physical, error-correction, and logical computation layers of the quantum stack, and demonstrate that spin-qubit shuttling architectures are a viable and flexible substrate for scalable fault-tolerant quantum computation.
The theoretical impediments of quantum computing to the large-scale implementation are inherently noise, decoherence, and inefficiency of the current fault-tolerant schemes. Although quantum hardware and error detection methods have made great advancements, existing methods largely use fixed logic qubit simulations and fixed noise models, which are inefficient at responding to dynamically changing noise models and do not scale. To curb this shortcoming, there is a need to have a framework that incorporates flexibility, statistical intelligence, and system optimization. In this paper, a dynamically adaptive logic qubit architecture is proposed based on a statistical model that can be used to achieve fault-tolerant quantum computing on a scale. The framework makes use of probabilistic noise modeling, real-time feedback-based reconfiguration in the continuous optimization of logical qubit structures and error correction schemes. The proposed architecture reduces the error propagation and reduces resource overhead by adding statistical inference using adaptive control mechanisms. Large-scale simulation experiments show that the given approach can suppress logical errors up to 28 percent better and reduce qubit overhead by 35 percent in comparison to the traditional fault-tolerant models that are based on static models and fault-tolerance in different noise levels. Moreover, the framework has a stable performance when the size of the system is growing, which indicates its stability and scalability. These results put dynamically adaptive logical qubit architectures as a potentially fruitful direction towards real-world and scalable quantum computing, and can be used in optimization, secure communication, and modeling of complex systems.