To run a practical size of quantum program, computer architects have been making tremendous efforts to realize fault-tolerant quantum computing (FTQC) which constructs a fault-tolerant logical qubit by correcting many erroneous physical qubits during runtime. However, it is extremely challenging to build a full-stack FTQC system consisting of heterogeneous stacks, where each stack incurs unique challenges regarding the fault tolerance and the interplay of the challenges incurs very complicated overall design choice problem. Therefore, computer architects must fully understand stack-specific optimizations and their system-level trade-offs, and resolve all the challenges together. In this article, we first introduce critical design challenges in architecting an FTQC system built on the superconducting technology, and then present our research outcomes to resolve the challenges to build an FTQC system realizing thousands of logical qubits. We also outline near-future directions to resolve the remaining challenges and provide insights toward realizing more scalable future FTQC systems.
To run a practical size of quantum program, computer architects have been making tremendous efforts to realize fault-tolerant quantum computing (FTQC) which constructs a fault-tolerant logical qubit by correcting many erroneous physical qubits during runtime. However, it is extremely challenging to build a full-stack FTQC system consisting of heterogeneous stacks, where each stack incurs unique challenges regarding the fault tolerance and the interplay of the challenges incurs very complicated overall design choice problem. Therefore, computer architects must fully understand stack-specific optimizations and their system-level trade-offs, and resolve all the challenges together. In this article, we first introduce critical design challenges in architecting an FTQC system built on the superconducting technology, and then present our research outcomes to resolve the challenges to build an FTQC system realizing thousands of logical qubits. We also outline near-future directions to resolve the remaining challenges and provide insights toward realizing more scalable future FTQC systems.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Fault-tolerant quantum computing (FTQC) has the potential to reliably execute complex calculations by overcoming the problems raised from the errors and noise inherent in quantum systems. This paper builds upon a 2025 report issued by the National Academy of Technologies of France. After recalling the principles that underly the so-called "quantum advantage," the use of error-correcting codes in the design of fault-tolerant quantum computers is discussed. Also explored are the five most advanced physical technologies that can be used to build such computers and the challenges of scaling up to a sufficient size to run useful applications. After highlighting the limits of monolithic qubit integration, the focus turns to increasing the number of available physical qubits by interconnecting several quantum processing modules. The paper concludes with a discussion of technical and economic environments, their performance benchmarks, and their future coexistence with other computing technologies and with supercomputers.
Fault tolerance is an indispensable prerequisite for constructing large-scale universal quantum computers. Drawing philosophies from classical computer architecture, this paper presents a hardware-agnostic three-layer high-level architectural framework for generic fault-tolerant quantum computation. Guided by the real execution workflows of fault-tolerant quantum algorithms, the proposed model is decoupled from specific physical qubit hardware platforms and quantum error correction codes, serving as a universal abstract standard rather than a platform-specific implementation scheme. Special attention is devoted to the intermediate Fault-Tolerance Layer, which serves as the architectural bridge between application-level logical programs and hardware-level execution. We systematically characterize its five internal components, the interfaces and data exchanged among them, and the execution, correction, and adaptation paths that together enable logical synthesis, fault-tolerant resources management, decoding, and runtime fault-tolerant control. An end-to-end example is further provided to illustrate the full-stack operating pipeline of fault-tolerant quantum algorithms under this framework. Given the increasing emphasis on modular, heterogeneous, and cross-layer fault-tolerant quantum systems, our architecture provides a unified foundational model for organizing such designs.
The limited qubit resources of current quantum processing units (QPUs), together with their susceptibility to operational imperfections, environmental noise, and error propagation, not only degrade computational fidelity but also constrain the scalability required for utility-scale quantum computing. Consequently, the transition from monolithic architectures to distributed quantum computing (DQC), supported by distributed quantum error-correcting codes (QECCs), is emerging as a promising paradigm for large-scale fault-tolerant quantum computing (FTQC). This transition represents a full-stack challenge that requires coordinated advances in quantum architecture, fault-tolerant gate operations, and classical–quantum co-processing and control. In this paper, we review the theoretical foundations and practical realization of large-scale FTQC. We first explore major families of QECCs, including topological, qLDPC, subsystem, and dynamical codes, with emphasis on code construction, syndrome extraction, and decoding. We then review the implementation of fault-tolerant universal gate sets at the physical and logical levels, followed by entanglement generation, distribution, and purification for distributed architectures. Finally, we outline open challenges and future research directions in theory, architecture, and implementation, highlighting the role of distributed fault-tolerant designs in next-generation utility-scale quantum computing.
Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
Executing quantum applications with quantum error correction (QEC) faces the gate non-universality problem imposed by the Eastin-Knill theorem. As one resource-time-efficient solution, code switching changes the encoding of logical qubits to implement universal logical gates. Unfortunately, it is still unclear how to perform full-stack fault-tolerant quantum computing (FTQC) based on the changeable logical qubit. Specifically, three critical problems remain unsolved: a) how to implement the dynamic logical qubit on hardware; b) how to determine the appropriate timing for logical qubit varying; c) how to improve the overall system performance for programs of different features. To overcome those design problems, We propose CECQ, to explore the large design space for FTQC based on changeable logical qubits. Experiments on various quantum programs demonstrate the effectiveness of CECQ.