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Arabian Journal for Science and Engineering

The Coherence Challenge: Foundations and Advancements in Superconducting Quantum Circuits

Saleem G. Rao

Published Feb 5, 2026• 1 citation
Publisher
DOI
10.1007/s13369-025-10979-0

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This thesis explores novel strategies for advancing superconducting quantum computing through a series of experimental investigations and device innovations. Grounded in the development of circuit quantum electrodynamics, the work addresses the challenges posed by the limitations of coherent control, coherence time and scaling of superconducting qubits. Focusing on transmon qubits, the thesis first reviews the foundational principles of circuit quantum electrodynamics and the critical role of the transmon in achieving robust qubit performance. Three experimental studies form the core of this work. The first study demonstrates a universal quantum gate set for strongly coupled transmons. By exploiting the residual ZZ interaction, the work introduces a novel two-axis gate protocol for single-qubit operations and implements both CZ and CNOT gates with high fidelities, highlighting the potential for fast, low-error quantum operations in the strong coupling regime. The second study investigates a dual-rail qubit architecture using parametrically coupled transmons, showcasing a hardware-efficient approach to quantum error correction. This experiment converts single-photon loss errors into detectable erasures and leverages mid-circuit detection to enhance qubit coherence, thereby advancing fault-tolerant quantum computing schemes in the NISQ era. The final study focuses on the development of merged-element transmons (MET) and their FinMET variants. By integrating the Josephson junction and shunt capacitor into a single trilayer device, these innovations achieve a dramatic reduction in device footprint while addressing loss channels through advanced materials engineering, ultimately paving the way for scalable, high-coherence quantum circuits. Collectively, these contributions demonstrate significant progress in quantum gate design, error mitigation, and qubit architecture, offering promising routes toward the realization of largescale, fault-tolerant quantum computers
The performance of superconducting quantum circuits for quantum computing has advanced tremendously in recent decades; however, a comprehensive understanding of relaxation mechanisms does not yet exist. In this work, we utilize a multimode approach to characterizing energy losses in superconducting quantum circuits, with the goals of predicting device performance and improving coherence through materials, process, and circuit design optimization. Using this approach, we measure significant reductions in surface and bulk dielectric losses by employing a tantalum-based materials platform and annealed sapphire substrates. With this knowledge we predict the relaxation times of aluminum- and tantalum-based transmon qubits, and find that they are consistent with experimental results. We additionally optimize device geometry to maximize coherence within a coaxial tunnel architecture, and realize on-chip quantum memories with single-photon Ramsey times of 2.0 - 2.7 ms, limited by their energy relaxation times of 1.0 - 1.4 ms. These results demonstrate an advancement towards a more modular and compact coaxial circuit architecture for bosonic qubits with reproducibly high coherence.