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Hardware-Aware Quantum Error Correction and Architectural Designs for Quantum Computers

Gözde Üstün

Published Feb 3, 2026• 0 citations
Publisher

Abstract

Quantum Error Correction (QEC) is often idealized as hardware-agnostic, yet its practical implementations must be tailored to the underlying system. The nuclear and electron spins of donor atoms in silicon constitute a physical platform that offers long coherence times, a well-characterized Hamiltonian, precise quantum control, and a readout mechanism that uses the electron as an ancilla. In this thesis, we reconsider the fundamentals of QEC, from gates to architecture, showing how they can be tailored to donor spins, while exploring different architectural paradigms using donor spins. Motivated by the hardware’s native Hamiltonian and ancilla-assisted readout, we design Single-Step Parity Check (SSPC) gates that perform parity checks directly, bypassing 1- and 2-qubit decompositions and improving circuit error tolerance. We developed a numerical workflow using experimental process matrices to evaluate these operations and quantified cumulative losses in a two-body parity-check circuit by tracking 1- and 2-qubit gate error rates on a two-phosphorus, one-electron silicon chip. GRAPE-optimized pulses were generated for both standard and SSPC-based circuits on the same platform, showing SSPC gates outperform and offer hardware-aware QEC implementations. We next explore antimony, a high-spin donor, as a candidate for photonic quantum computing. With a nuclear spin of 7/2, antimony has eight energy levels which, when coupled to a microwave cavity, can emit a single-photon across eight modes. This supports third quantization, where (near-)deterministic photon entanglement is achieved by spreading single photons across many modes and sending each mode to a party, creating entanglement without photon–photon interactions or probabilistic gates. We proposed an experiment for the simplest realization of third quantization, where an antimony donor produces two independent 8-mode photons, distributed to parties, creates a Bell state between 56 random pairs with 87.5% efficiency. We then explored high-dimensional fusion operations for fusing qudit cluster states. Focusing on Type-II fusion, a central component of measurement-based quantum computing, we derived the most efficient high-dimensional protocol known to date — a 723-fold improvement over the best previously known protocol in the case of d = 5. To further enhance success probability of fusion, we introduced extra-dimensional corrections framework. We unified these insights to design two approaches for qudit graph state generation using antimony donors. One is for the direct generation of arbitrary graph states from coupled antimony donors, where two antimony atoms share a single electron, forming 128-dimensional Hilbert space, while the other focuses on the generation of linear graph states from a single antimony donor, followed by high-dimensional fusion operations to construct graph states in arbitrary shapes. We compared the two schemes in terms of their capabilities and potential for scalability.

DOI
10.26190/unsworks/31990

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Quantum Error Correction (QEC) is often idealized as hardware-agnostic, yet its practical implementations must be tailored to the underlying system. The nuclear and electron spins of donor atoms in silicon constitute a physical platform that offers long coherence times, a well-characterized Hamiltonian, precise quantum control, and a readout mechanism that uses the electron as an ancilla. In this thesis, we reconsider the fundamentals of QEC, from gates to architecture, showing how they can be tailored to donor spins, while exploring different architectural paradigms using donor spins. Motivated by the hardware’s native Hamiltonian and ancilla-assisted readout, we design Single-Step Parity Check (SSPC) gates that perform parity checks directly, bypassing 1- and 2-qubit decompositions and improving circuit error tolerance. We developed a numerical workflow using experimental process matrices to evaluate these operations and quantified cumulative losses in a two-body parity-check circuit by tracking 1- and 2-qubit gate error rates on a two-phosphorus, one-electron silicon chip. GRAPE-optimized pulses were generated for both standard and SSPC-based circuits on the same platform, showing SSPC gates outperform and offer hardware-aware QEC implementations. We next explore antimony, a high-spin donor, as a candidate for photonic quantum computing. With a nuclear spin of 7/2, antimony has eight energy levels which, when coupled to a microwave cavity, can emit a single-photon across eight modes. This supports third quantization, where (near-)deterministic photon entanglement is achieved by spreading single photons across many modes and sending each mode to a party, creating entanglement without photon–photon interactions or probabilistic gates. We proposed an experiment for the simplest realization of third quantization, where an antimony donor produces two independent 8-mode photons, distributed to parties, creates a Bell state between 56 random pairs with 87.5% efficiency. We then explored high-dimensional fusion operations for fusing qudit cluster states. Focusing on Type-II fusion, a central component of measurement-based quantum computing, we derived the most efficient high-dimensional protocol known to date — a 723-fold improvement over the best previously known protocol in the case of d = 5. To further enhance success probability of fusion, we introduced extra-dimensional corrections framework. We unified these insights to design two approaches for qudit graph state generation using antimony donors. One is for the direct generation of arbitrary graph states from coupled antimony donors, where two antimony atoms share a single electron, forming 128-dimensional Hilbert space, while the other focuses on the generation of linear graph states from a single antimony donor, followed by high-dimensional fusion operations to construct graph states in arbitrary shapes. We compared the two schemes in terms of their capabilities and potential for scalability.
Abstract A key requirement for an effective quantum error correction (QEC) scheme is that the physical qubits have error rates below a certain threshold. The value of this threshold depends on the details of the specific QEC scheme, and its hardware-level implementation. This is especially important with parity-check circuits, which are the fundamental building blocks of QEC codes. The standard way of constructing the parity check circuit is using a universal set of gates, namely sequential CNOT gates, single-qubit rotations and measurements. We exploit the insight that a QEC code does not require universal logic gates, but can be simplified to perform the sole task of error detection and correction. By building gates that are fundamental to QEC, we can boost the threshold and ease the experimental demands on the physical hardware. We present a rigorous formalism for constructing and verifying the error behavior of these gates, linking the physical measurement of a process matrix to the abstract error models commonly used in QEC analysis. This allows experimentalists to directly map the gates used in their systems to thresholds derived for a broad-class of QEC codes. We give an example of these new constructions using the model system of two nuclear spins, coupled to an electron spin, showing the potential benefits of redesigning fundamental gate sets using QEC primitives, rather than traditional gate sets reliant on simple single and two-qubit gates.
The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topological quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel-posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically separated control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited.
Building fault-tolerant quantum computers with large numbers of logical qubits requires both scalable hardware architectures and error-correcting codes that make efficient use of physical qubits. Photonic interconnects address both of these challenges by allowing the physical qubits to be distributed across multiple processors while providing the non-local connectivity necessary to implement resource-efficient codes such as high-rate quantum low-density parity-check (qLDPC) codes. A key requirement for realising this architecture is the ability to perform stabiliser measurements between remote processors, which has not previously been demonstrated experimentally. Here we report the first experimental demonstration of distributed quantum error detection and correction. We generate entanglement between network qubits in two separate trapped-ion processors and use it to perform remote syndrome measurements on data qubits. We first realise a distributed [[2, 1, 1]] repetition code, detecting phase-flip errors on a logical qubit encoded across the two modules in real time and suppressing logical errors. We then combine these mid-circuit syndrome measurements with real-time feedforward to actively correct arbitrary single-qubit Pauli errors on a distributed Bell state. These results provide an experimental foundation for quantum error correction (QEC) across modular quantum architectures.
Universal quantum computers require a large network of qubits robust against errors. Recent theoretical and experimental studies on donor nuclear spins in silicon, engineered on semiconductor platforms compatible with industrial fabrication, show their coherent behavior and potential for scalability. Here we present a hardware-efficient quantum protocol that corrects phase flips of a nuclear spin using explicit experimentally feasible operations. We introduce moment angular system encoding that uses the large Hilbert space provided by the nuclear spin of the donor to encode the information and employ the electron spin of the donor as an ancilla for error correction. Simulations using present-day experimental manipulation fidelities predict significant improvement in logical qubit fidelity over existing spin quantum-error-correction protocols. These results provide a realizable blueprint for a corrected spin-based qubit.
Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024
Quantum error correction of a grid-state qubit with state preparation and measurement errors below 10−310^{-3}10−3
Grid state qubits offer a hardware-efficient approach to large-scale fault-tolerant quantum computing. They access the information redundancy required for quantum error correction by exploiting the large Hilbert space naturally available in harmonic oscillators. Superconducting architectures are particularly suitable to implement grid state qubits due to their fast and high-fidelity operations. Grid states in superconducting circuits enable quantum error correction (QEC) with performance beyond break-even. However, the state preparation and measurements (SPAM) errors of grid states has been a significant limitation to computational performances. In this work, we leverage high-performance QEC to enable repeat-until-success state preparation of both cardinal and magic states of the single-mode grid-state qubit. We combine this with an improved measurement protocol that corrects for both finite-energy envelope and auxiliary qubit readout errors, and increases robustness to photon loss. Our experiments, using both techniques, achieve a combined state-preparation and measurement error below 10−310^{-3}10−3. This represents two orders-of-magnitude improvement over the state of the art, bringing this platform on par with standard SPAM error levels measured in transmon qubits.