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IEEE Transactions on Applied Superconductivity

A Finite State Automaton for the Tsetlin Machine Using High-Capacity Resettable D Flip-Flop Cells

Zeyu Han, Nobuyuki Yoshikawa, Yuki Yamanashi

Published Jan 27, 2026• 0 citations
Publisher

Abstract

Single Flux Quantum (SFQ) circuits provide ultrafast operation and low power consumption, making them attractive candidates for machine learning accelerators. The Tsetlin Machine (TM) is a low-complexity and highly interpretable architecture, organized as a voting system of propositional clauses. In the TM, an ensemble of finite-state automata (FSAs), called Tsetlin automata, independently decides whether to include or exclude specific literals. The chosen literals are assembled into propositional clauses that collectively form the voting system, while each FSA updates its state based on rewards or penalties determined by the prediction outcome. However, existing FSA designs for TM based on SFQ circuits still suffer from either a narrow margin or excessive circuit area. To achieve compact and stable state transitions using SFQ circuits, we designed High-Capacity Resettable D Flip-Flop (HC-RDFF) cells by cascading storage loops. The proposed FSA was implemented using two HC-RDFFs to store the include and exclude states, respectively. The FSA with 16 states requires only 395 Josephson junctions with a static power of approximately 128 μW, exhibiting a bias margin of −21% to +25% at low speed and a maximum operating frequency of 20 GHz in simulation. We fabricated the HC-RDFF and the FSA using a 10 kA/cm² Nb four-layer superconducting process and verified their correct operation through low-speed measurements. The number of FSA states can be increased simply by extending the cascaded storage loops in the HC-RDFFs. We expect the proposed FSA to be suitable for constructing stable TM systems based on SFQ circuits with reduced hardware costs.

DOI
10.1109/tasc.2026.3657683

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Single Flux Quantum (SFQ) circuits provide ultrafast operation and low power consumption, making them attractive candidates for machine learning accelerators. The Tsetlin Machine (TM) is a low-complexity and highly interpretable architecture, organized as a voting system of propositional clauses. In the TM, an ensemble of finite-state automata (FSAs), called Tsetlin automata, independently decides whether to include or exclude specific literals. The chosen literals are assembled into propositional clauses that collectively form the voting system, while each FSA updates its state based on rewards or penalties determined by the prediction outcome. However, existing FSA designs for TM based on SFQ circuits still suffer from either a narrow margin or excessive circuit area. To achieve compact and stable state transitions using SFQ circuits, we designed High-Capacity Resettable D Flip-Flop (HC-RDFF) cells by cascading storage loops. The proposed FSA was implemented using two HC-RDFFs to store the include and exclude states, respectively. The FSA with 16 states requires only 395 Josephson junctions with a static power of approximately 128 μW, exhibiting a bias margin of −21% to +25% at low speed and a maximum operating frequency of 20 GHz in simulation. We fabricated the HC-RDFF and the FSA using a 10 kA/cm² Nb four-layer superconducting process and verified their correct operation through low-speed measurements. The number of FSA states can be increased simply by extending the cascaded storage loops in the HC-RDFFs. We expect the proposed FSA to be suitable for constructing stable TM systems based on SFQ circuits with reduced hardware costs.
Due to their high-speed operation and low power consumption, single flux quantum (SFQ) circuits are promising technologies for integrated circuits. However, current superconducting fabrication limitations impose strict area constraints, challenging the construction of large-scale systems. Unary computing (UC) encodes numerical values by concentrating all “1”s at the beginning of a bit sequence. This approach enables arithmetic operations with fewer logic gates, thereby improving the area efficiency. In this study, we propose a novel high-capacity D flip-flop (HC-DFF) cell for UC-based SFQ circuits that achieves high-density data registration while preserving UC encoding. The HC-DFF employs a cascaded storage loop structure in which each loop sequentially stores one flux quantum, avoiding the margin deterioration associated with storing multiple flux quanta in a single loop. Simulation shows that the proposed HC-DFF achieves a bias margin of –20.8% to +32.7% and supports read/write operations above 100 GHz. We fabricated the HC-DFF using a 10 kA/cm² Nb four-layer superconducting process and verified its operation through low-speed measurements. The HC-DFF offers enhanced scalability and stability while reducing the number of required Josephson junctions by 83.3% per bit compared to conventional DFF-based shift registers for saving UC signals. For short unary sequences of less than 31 bits, it retains an advantage over storing binary data with equivalent precision using conventional DFF-based shift registers.
Tsetlin Machines (TMs) learn interpretable Boolean clauses using finite-state automata. We introduce the Quantum-Logic Tsetlin Machine (QL-TM), which replaces Boolean literals with quantum propositions represented by projectors while retaining classical include/exclude automata. Clauses are restricted to commuting measurement contexts and activate through the Born probability of their joint projector. We prove an exact reduction to ordinary Boolean TM clauses in diagonal computational-basis contexts and connect Pauli-projector clauses to stabilizer and syndrome semantics. Controlled experiments on Bell states, phase-flip syndromes, randomized 16-class stabilizer tasks, mixed literal pools, context-budget ablations, and finite-shot noise show that correct non-diagonal contexts recover physically meaningful clauses, while diagonal or wrong contexts lose the relevant phase/syndrome information. The context-budget results closely follow the predicted separability ladder 2^(b-k) as true stabilizer generators are removed. The contribution is a controlled bridge between Tsetlin clause learning and quantum logic, not a claim of quantum advantage.
A promising application of a single-flux quantum (SFQ) circuit is read-out circuitry for a multi-channel superconductive sensor array. In such applications, the SFQ read-out circuit is expected to operate outside a magnetic shield. We investigated an SFQ circuit structure, which is tolerant to an external magnetic field, using the AIST 2.5kA/cm2 Nb standard 2 process, which has four Nb wiring layers including the ground plane. By covering the entire circuit using an upper Nb wiring layer called the control (CTL) layer, the influences of the external magnetic field on the SFQ circuit operation can be avoided. We experimentally evaluated the sheet inductance of the wiring layer underneath the CTL shielding layer to design a magnetic-field-tolerant SFQ circuit. We implemented and measured test circuits comprising toggle flip-flops (TFFs) to evaluate their magnetic field tolerances. The operating margin and maximum operating frequency of the designed TFF did not deteriorate with increases in the magnetic field applied to the test circuit, whereas the operating margin of the conventional TFF was reduced by applying the magnetic field. We have also demonstrated the high-speed operation of the designed TFF operated in an unshielded environment at a frequency of up to 120GHz with a wide operating margin.
A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π -shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π -shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π -shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and π -shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0- π Josephson junctions.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.