Quantum computing’s burgeoning influence extends across disciplines such as cryptography, machine learning, and optimization problems, promising computational advantages that surpass the limitations of classical approaches. Despite their theoretical potential, the fidelity of quantum algorithms is compromised by the detrimental effects of noise and decoherence, resulting in substantial errors during the execution of quantum circuits. Although Hardware Efficient Ansatz (HEA) circuits are designed to generate pure quantum states, ideally represented by state vectors, the presence of noise in physical quantum devices transforms these pure states into mixed states, necessitating the use of density matrices and thereby complicating error analysis. Computing noise induced errors in density matrices with high precision remains computationally demanding because of the exponential scaling of the underlying mathematical operations. However, the shallow depth and near term compatibility of HEA circuits make them well suited for variational quantum methods, offering a practical approach within the constraints of current hardware. This paper proposes an OpenMP based parallelization methodology designed to enhance the computational efficiency of noise error estimation in HEA circuits. The integration of classical parallel computing techniques into quantum circuit simulation presents a viable approach to improving the scalability and precision of noise aware quantum computing research. Experimental results indicate an average speedup of approximately 22.34 for pure states and 3.89 for mixed states across varying numbers of qubits.
Quantum computing’s burgeoning influence extends across disciplines such as cryptography, machine learning, and optimization problems, promising computational advantages that surpass the limitations of classical approaches. Despite their theoretical potential, the fidelity of quantum algorithms is compromised by the detrimental effects of noise and decoherence, resulting in substantial errors during the execution of quantum circuits. Although Hardware Efficient Ansatz (HEA) circuits are designed to generate pure quantum states, ideally represented by state vectors, the presence of noise in physical quantum devices transforms these pure states into mixed states, necessitating the use of density matrices and thereby complicating error analysis. Computing noise induced errors in density matrices with high precision remains computationally demanding because of the exponential scaling of the underlying mathematical operations. However, the shallow depth and near term compatibility of HEA circuits make them well suited for variational quantum methods, offering a practical approach within the constraints of current hardware. This paper proposes an OpenMP based parallelization methodology designed to enhance the computational efficiency of noise error estimation in HEA circuits. The integration of classical parallel computing techniques into quantum circuit simulation presents a viable approach to improving the scalability and precision of noise aware quantum computing research. Experimental results indicate an average speedup of approximately 22.34 for pure states and 3.89 for mixed states across varying numbers of qubits.
Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities. Building upon prior work, we introduce an error- and topology-aware method for mapping multiple independent circuits onto disjoint regions of a single large-scale QPU for parallel circuit execution. For applications with many similarly sized circuits, such as observable estimation for Hamiltonian simulation, this approach can reduce billed QPU execution time, with ideal speedup proportional to the number of usable partitions. We demonstrate the approach on IBM's 156-qubit ibm_boston processor using standard QED-C benchmark and Hamiltonian-based observable-estimation workloads. Compared with standard sequential execution, parallel execution reduces billed execution time by 3.5-5.5x while retaining 83-92% of the sequential fidelity. We further evaluate the scaling of parallel circuit execution using GPU-accelerated classical simulation, distributing measurement circuits across GPUs via MPI. Using CUDA-Q on the NERSC Perlmutter system, we achieve up to 13.8x speedup on 16 GPUs (86% parallel efficiency) for an H2 electronic-structure simulation, with scaling evaluated across multiple Hamiltonians and circuit counts. These results provide an indication of the performance ceiling that parallel execution on future quantum hardware may eventually approach. Both execution modes are implemented as a runtime option within the QED-C Application-Oriented Benchmark suite. Together, the results show that circuit-level parallelism can reduce execution cost on current quantum hardware and simulation time on GPU clusters, with the potential for greater benefits as device quality and qubit counts increase.
Quantum computing not only holds the potential to solve long-standing problems in quantum physics, but also to offer speed-ups across a broad spectrum of other fields. Access to a computational space that incorporates quantum effects, such as superposition and entanglement, enables the derivation of promising quantum algorithms for important tasks, including preparing the ground state of a quantum system or predicting its evolution over time. Successfully tackling these tasks promises insights into significant theoretical and technological questions, such as superconductivity and the design of new materials. The aim of quantum algorithms is to use a series of quantum operations in a quantum circuit to solve a problem beyond the reach of classical computers. However, the noise and limited scale of current quantum computers restricts these circuits to moderate sizes and depths. As a result, many prominent algorithms are currently infeasible to run for problem sizes of practical interest. In response, recent research focused on variational quantum algorithms, which allow the selection of circuits that act within a quantum device's capabilities. Yet, these algorithms can require the execution of a large number of circuits, leading to prohibitively long computation times. This doctoral thesis develops two main techniques to reduce these quantum computational resource requirements, with the goal of scaling up application sizes on current quantum processors. The first approach is based on stochastic approximations of computationally costly quantities, such as quantum circuit gradients or the quantum geometric tensor (QGT). The second method takes a different perspective on the QGT, leading to a potentially more efficient description of time evolution on current quantum computers. Both techniques rely on maintaining available information and only computing necessary corrections, instead of re-computing possibly redundant data. The main focus of application for our algorithms is the simulation of quantum systems, broadly defined as including the preparation of ground and thermal states, and the real- and imaginary-time propagation of a system. The developed subroutines, however, can further be utilized in the fields of optimization or machine learning. Our algorithms are benchmarked on a range of representative models, such as Ising or Heisenberg spin models, both in numerical simulations and experiments on the hardware. In combination with error mitigation techniques, the latter is scaled up to 27 qubits; into a regime that variational quantum algorithms are challenging to scale to on noisy quantum computers without our algorithms.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Hybridizing machine learning (ML) with quantum computing has become an attractive strategy to increase computational power on Noisy Intermediate Scale Quantum (NISQ) devices. Although these can be potentially quantum advantage devices, their qubit numbers and noise are bounded and there are challenges when it comes to practical quantum circuit realization. This work concentrates on the creation of optimized quantum circuits via ML-based strategies, to enhance the performance of the circuits, to reduce the error rate and to accommodate the particular noise profile of the hardware of NISQ devices. The resulting suboptimal mappings with little or no consideration of noise and hardware topology in traditional quantum compilers can ruin the fidelity of quantum algorithm. Leveraging machine learning, and specifically reinforcement and supervised learning methods, our method learns to optimize compilation strategy for specific quantum hardware architecture. The paper proposes a framework that uses machine learning models to predict qubit mappings, gate decompositions, and transpilation paths that minimize gate depth and error accumulation. We also investigate transfer learning methods for propagating the learned compilation strategies to novel NISQ machines. Such methods are empirically validated on both simulated and real quantum hardware backends, providing evidence of circuit depth, execution time and error reductions. The results show that ML-assisted compilation can achieve better success probabilities for benchmark quantum algorithms like VQE and QAOA than conventional compilers. Furthermore, the work examines the interpretability of ML models providing hardware-aware optimization recommendations and understanding the noise patterns and methods of error correction. Our work highlights the key role of ML for transferring between theoretical quantum algorithms and their practical NISQ implementations. This integration boosts the immediate applicability of existing quantum devices and provides a basis for adaptive and scalable likelihood-based compilation for the era of fault-tolerant quantum computation. Our results motivate further investigation of hybrid classical-quantum workflows, in which ML iteratively improves compilation in accordance with changing hardware noise and capabilities. By improving quantum circuit compilation onNISQ computers, this work is taking steps toward the realization of quantum advantage in application scenarios such as optimization, cryptography, and quantum simulation without needing to wait for fully fault-tolerant large-scale quantum computers.
Abstract Resource-efficient, low-depth implementations of quantum circuits remain a promising strategy for achieving reliable and scalable computation on quantum hardware, as they reduce gate resources and limit the accumulation of noisy operations. Here, we propose a low-depth implementation of a class of Hadamard test circuits, complemented by the development of a parameterized quantum ansatz specifically tailored for variational algorithms that exploit the underlying Hadamard test framework. Our findings demonstrate a significant reduction in single- and two-qubit gate counts, suggesting a reliable circuit architecture for noisy intermediate-scale quantum devices. Building on this foundation, we tested our low-depth scheme to investigate the expressive capacity of the proposed parameterized ansatz in simulating nonlinear Burgers’ dynamics. The resulting variational quantum states faithfully capture the shockwave feature of the turbulent regime and maintain high overlaps with classical benchmarks, underscoring the practical effectiveness of our framework. Furthermore, we evaluate the effect of hardware noise by modeling the error properties of real quantum processors and by executing the variational algorithm on a trapped-ion-based IBEX Q1 device. The outcomes of our demonstrations highlight the resilience of our low-depth scheme in the turbulent regime, consistently preparing high-fidelity variational states that exhibit strong agreement with classical benchmarks. Our work contributes to the advancement of resource-efficient strategies for quantum computation, offering a robust framework for tackling a range of computationally intensive problems across numerous applications.
The rapid advancement of quantum computing has created new opportunities for solving computationally intensive problems across diverse fields such as optimization, physical system simulation, and machine learning. However, practical implementation on Noisy Intermediate-Scale Quantum (NISQ) devices remains challenging due to hardware limitations including noise, decoherence, and restricted qubit connectivity. A fundamental constraint further complicating this effort is that all quantum operations must be unitary, while many real-world problems are naturally expressed in non-unitary forms. This discrepancy necessitates novel techniques for transforming non-unitary mathematical structures into unitary or Hamiltonian representations compatible with quantum hardware.This thesis proposes a unified framework for converting structured, sparse, or otherwise non-unitary classical matrices into unitary forms that can be executed efficiently on NISQ devices. The methodology introduces general transformation strategies such as linear combinations of unitaries, structured embeddings, and resource-aware circuit construction, enabling the deployment of quantum algorithms without incurring prohibitive overhead. Each technique is developed with an emphasis on preserving problem structure, minimizing circuit depth, and ensuring compatibility with IBM’s NISQ hardware. The proposed frameworks are validated through theoretical analysis and quantum simulations, with performance benchmarks based on gate count, circuit fidelity, convergence behavior, and scalability. This work demonstrates how non-unitary formulations arising in various computational contexts can be systematically adapted for quantum execution, advancing the practical utility of NISQ-era devices.