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Irish Signals and Systems Conference

Multi-Stage Bit-Flipping Decoder Design for Quantum Error-Correcting Codes

Patrick J. Moxom, Mark F. Flanagan

Published Jun 9, 2025• 0 citations
Publisher

Abstract

This paper proposes the use of simple bit-flipping (BF) methods as a post processor for decoding quantum low-density parity check codes (qLDPC) with message passing (MP). Specifically, min-sum (MS) is used as the MP method for the first stage of the multi-stage decoder. Two methods are proposed that modify the low-complexity Gallager’s algorithm (GA). First, a weighted bit-flipping (WBF) method is developed using soft information from the MP stage. Secondly, GA is modified with a random bit-flipping (RBF) approach. Early stopping and loop detector stage switching methods are used to enhance the performance of the BF stage. These methods are shown to significantly reduce the error floor of the first stage while also being less complex than alternative multi-stage decoders.

DOI
10.1109/issc67739.2025.11291312

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This paper proposes the use of simple bit-flipping (BF) methods as a post processor for decoding quantum low-density parity check codes (qLDPC) with message passing (MP). Specifically, min-sum (MS) is used as the MP method for the first stage of the multi-stage decoder. Two methods are proposed that modify the low-complexity Gallager’s algorithm (GA). First, a weighted bit-flipping (WBF) method is developed using soft information from the MP stage. Secondly, GA is modified with a random bit-flipping (RBF) approach. Early stopping and loop detector stage switching methods are used to enhance the performance of the BF stage. These methods are shown to significantly reduce the error floor of the first stage while also being less complex than alternative multi-stage decoders.
We present two general multi-stage (MS) bit-flipping (BF) decoding algorithms for low-density parity-check (LDPC) codes. Both algorithms consist of soft-decision (SD) and hard-decision BF decoding parts. In comparison with known MS LDPC decoders, our approach is much simpler as all stages share the same BF structure. The only complexity increase is due to the use of an adaptive stage-switching (SS) mechanism which gives near-optimal SS timing. A new design issue we address is that the first-stage algorithm's parameter has to be re-tuned to achieve the optimal overall performance. The numerical results demonstrate that the proposed decoding methods can significantly improve the error-rate performance of the conventional SD BF decoders.
To improve the decoding speed and performance of Weighted Bit Flipping (WBF) decoding algorithm for Low Density Parity Check (LDPC) codes, a two-stage WBF algorithm with a multi-/single-bit switching mechanism is proposed. It first performs multi-bit flipping decoding in the first-stage decoder. When cyclic flipping is detected or the maximum flipping function value is less than zero, it switches to the second-stage decoder. Simulation results show that the proposed algorithm obtains gains both in average decoding iteration number and in decoding performance compared with the Sum of the Magnitude based WBF (SMWBF) and the Variable node updating based SMWBF (VSMWBF).
We propose a low latency hardware-friendly decoding framework for Calderbank-Shor-Steane (CSS) quantum low-density parity-check (QLDPC) codes under the depolarizing noise model. With a given latency constraint, the proposed decoder, referred to generally as the Turbo-XZ decoding algorithm utilizes the correlation of Pauli X and Z errors. In this framework, we introduce early stopping and switching decoders to meet latency constraints and improve error correction performance for different decoders including the bit-flip (BF), fixed BF (proposed hardware-friendly variant of BF), and normalized min-sum algorithm (nMSA). This decoding framework allows various tradeoffs in terms of latency, complexity, and decoding performance which are discussed briefly. Simulation results show that the BF-Turbo-XZ decoder performs close to (and beyond in some cases) the nMSA version with lower complexity and latency. Our proposed fixed BF approach reduces complexity with minimal performance degradation. For example with a generalized bicycle code, nMSA performs better for higher depolarizing values (p>0.02) at a higher cost, while low-complexity BF-Turbo-XZ decoders are better at low depolarizing values.
We propose a low latency hardware-friendly decoding framework for Calderbank-Shor-Steane (CSS) quantum lowdensity parity-check (QLDPC) codes under the depolarizing noise model. With a given latency constraint, the proposed decoder, referred to generally as the Turbo-XZ decoding algorithm utilizes the correlation of Pauli X and Z errors. In this framework, we introduce early stopping and switching decoders to meet latency constraints and improve error correction performance for different decoders including the bit-flip (BF), fixed BF (proposed hardware-friendly variant of BF), and normalized min-sum algorithm (nMSA). This decoding framework allows various tradeoffs in terms of latency, complexity, and decoding performance which are discussed briefly. Simulation results show that the BF-Turbo-XZ decoder performs close to (and beyond in some cases) the nMSA version with lower complexity and latency. Our proposed fixed BF approach reduces complexity with minimal performance degradation. For example with a generalized bicycle code, nMSA performs better for higher depolarizing values (p > 0.02) at a higher cost, while low-complexity BF-Turbo-XZ decoders are better at low depolarizing values.
Bit-flipping (BF) algorithms for decoding low-density parity-check (LDPC) codes have attracted considerable attention due to their low complexity and high parallelism. While recent improvements have enabled certain BF decoders to approach the performance of belief-propagation (BP) decoding, many of these enhancements rely on complex mechanisms such as loop detection, decoder switching, or costly online computations. In this paper, we propose enhanced BF decoding algorithms that integrate refined checksum weighting and flipping function designs. The proposed weighting scheme jointly exploits soft-valued channel information and hard-decision consistency to better reflect the reliability of each checksum, while maintaining negligible online complexity. Additionally, we propose a flipping function design that implicitly discourages repeated flipping by incorporating the accumulated flip count into its computation, thus suppressing decoding loops without requiring explicit loop detection or decoder switching. Simulation results demonstrate that the proposed decoding strategies yield notable performance gains over existing BF decoders, with only a minor complexity increase.
A natural relationship between weighted bit-flipping (WBF) decoding and message-passing decoding is explored. This understanding can help us develop a dual WBF decoding algorithm from one type of message-passing decoding algorithm and vice versa. For min-sum decoding, one can find that its dual WBF algorithm is the algorithm proposed by Jiang et al. For belief-propagation (BP) decoding, we propose a new WBF algorithm and show its performance advantage. For some high-rate low-density parity-check (LDPC) codes of large row weight, it is shown that the WBF algorithm proposed by Liu and Pados performs extraordinarily well. However, its dual message- passing decoding does not work well. Furthermore, we propose a parallel implementation framework for various WBF algorithms. Compared to serial implementations, various WBF algorithms in their parallel form converge significantly faster and often perform better.