Quantum computation simulators are essential to test algorithms when real quantum computers are not available. Schrödinger-style simulators store the full state vector that propagates through the circuit. Since the size of the state vector grow exponentially with more qubits, the memory is often a serious constraint for simulators on classical systems. In this work, we conduct an in-depth study of partitioning hybrid Schrödinger-Feynman (HSF) simulators. We develop formal definitions of such simulators and analyze their performance theoretically in terms of time and memory complexity. We propose an alternative version of partitioning HSF-simulators that enables parallelization over partitions, and show that it is useful for shallow circuits. We also arrive at a formula for the time consumption of HSF-simulators using checkpointing. We verify that our formulas coincide with experimental measurements.
Quantum computation simulators are essential to test algorithms when real quantum computers are not available. Schrödinger-style simulators store the full state vector that propagates through the circuit. Since the size of the state vector grow exponentially with more qubits, the memory is often a serious constraint for simulators on classical systems. In this work, we conduct an in-depth study of partitioning hybrid Schrödinger-Feynman (HSF) simulators. We develop formal definitions of such simulators and analyze their performance theoretically in terms of time and memory complexity. We propose an alternative version of partitioning HSF-simulators that enables parallelization over partitions, and show that it is useful for shallow circuits. We also arrive at a formula for the time consumption of HSF-simulators using checkpointing. We verify that our formulas coincide with experimental measurements.
Despite the continuous advancements in size and robustness of real quantum devices, reliable large-scale quantum computers are not yet available. Hence, classical simulation of quantum algorithms remains crucial for testing new methods and estimating quantum advantage. Pushing classical simulation methods to their limit is essential, particularly due to their inherent exponential complexity. Besides the established Schrödinger-style full statevector simulation, so-called Hybrid Schrödinger-Feynman (HSF) approaches have shown promise to make simulations more efficient. HSF simulation employs the idea of “cutting” the circuit into smaller parts, reducing their execution times. This, however, comes at the cost of an exponential overhead in the number of cuts. Inspired by the domain of Quantum Circuit Cutting, we propose an HSF simulation method based on the idea of “joint cutting” to significantly reduce the aforementioned overhead. This means that, prior to the cutting procedure, gates are collected into “blocks” and all gates in a block are jointly cut instead of individually. We investigate how the proposed refinement can help decrease simulation times and highlight the remaining challenges. Experimental evaluations show that “joint cutting” can outperform the standard HSF simulation by up to a factor ≈4000× and the Schrödinger-style simulation by a factor ≈200× for suitable instances. The implementation is available at https://github.com/cda-tum/mqt-qsim-joint-cutting.
Hybrid Schrodinger-Feynman (HSF) simulation offers an attractive memory-path tradeoff for exact quantum-circuit emulation, but its practical runtime is often dominated by exponential path growth from cross-boundary two-qubit gates. Existing GPU and FPGA quantum simulators are largely optimized for full-state Schrodinger execution and therefore do not align well with HSF's path-centric workflow. This paper presents HSF-S, a compiler-accelerator co-designed framework for exact HSF-based quantum circuit emulation. HSF-S lowers input circuits to an HSF-compatible basis, formulates a rank-aware effective path-cost model, and applies dependency-preserving reordering together with discounted-gain SWAP insertion to suppress recurring cross-boundary interactions while preserving exact circuit semantics. A regression-free selector guarantees that the compiled circuit never increases effective path cost relative to the naive lowered baseline. We further design a dedicated HSF-S accelerator and execution flow, and integrate them into a stand-alone processor for efficient per-path dual-slice evaluation and final accumulation without materializing the full state vector. Across 56 benchmark circuits, HSF-S matches reference amplitudes to within floating-point precision, reduces effective path cost by up to 90.0%, and substantially improves practical tractability, including representative timeout-to-sub-second reductions under a 1-hour budget. On the resulting compiled workloads, the HSF-S processor prototype delivers up to 4.34x additional speedup.
Owing to the exponential increase in computational complexity, the fast simulation of the large quantum circuit has become very difficult. This is an important challenge for the utilization of quantum computers because it is closely related to the verification of quantum computation by classical machines. The Hybrid Schrödinger-Feynman simulation seems to be a promising solution, but its application is very limited. To solve this drawback, we propose an improved simulation method based on graph partitioning. Experimental results show that our approach significantly reduces the simulation time of the Hybrid Schrödinger-Feynman simulation.
Many circuit simulators use either a Schrodinger-based or Feynman-based approach, which have complementary strengths. Schrödinger-based simulators maintain a state vector by synchronously updating it after each gate (or group of gates), ensuring time efficiency at the cost of exponential space. In contrast, Feynman-based simulators use low space but require high time to compute the sum of exponentially many independent Feynman paths. Because they treat paths as independent, Feynman-based simulators miss opportunities to take advantage of sparsity from destructive interference. In this paper, we present a hybrid Schrödinger-Feynman technique which takes advantage of sparsity by selectively synchronizing Feynman paths. Our hybrid technique partitions the circuit into kernels (groups of gates) and uses Feynman simulation within each kernel. It then synchronizes across the kernels by using Schrödinger-style simulation. We parallelize our approach by representing the simulation as a graph, leveraging state-of-the-art parallel graph algorithms. By selecting kernels carefully, we show that our approach can simulate hundreds of qubits efficiently (in both time and space) on just a single multicore node. In certain “sparse” circuits, we are able to improve running times by multiple orders of magnitude.
Classical simulations of quantum computations are vital for the future development of this emerging technology. To this end, decision diagrams have been proposed as a complementary technique which frequently allows to tackle the inherent exponential complexity of these simulations. In the worst case, however, they still cannot escape this complexity. Additionally, while other techniques make use of all the available processing power, decision diagram-based simulation to date cannot exploit the many processing units of today’s systems. In this work, we show that both problems can be tackled together by employing a hybrid Schrödinger-Feynman scheme for the simulation. More precisely, we show that realizing such a scheme with decision diagrams is indeed possible, we discuss the resulting problems in its realization, and propose solutions how they can be handled. Experimental evaluations confirm that this significantly advances the state of the art in decision diagram-based simulation— allowing to simulate certain hard circuits within minutes that could not be simulated in a whole day thus far.
Executing large quantum circuits is not feasible using the currently available NISQ (noisy intermediate-scale quantum) devices. The high costs of using real quantum devices make it further challenging to research and develop quantum algorithms. As a result, performing classical simulations is usually the preferred method for researching and validating large-scale quantum algorithms. However, these simulations require a huge amount of resources, as each additional qubit exponentially increases the computational space required. Distributed Quantum Computing (DQC) is a promising alternative to reduce the resources required for simulating large quantum algorithms at the cost of increased runtime. This study presents a comparative analysis of two simulation methods: circuit-splitting and full-circuit execution using distributed memory, each having a different type of overhead. The first method, using CutQC, cuts the circuit into smaller subcircuits and allows us to simulate a large quantum circuit on smaller machines. The second method, using Qiskit-Aer-GPU, distributes the computational space across a distributed memory system to simulate the entire quantum circuit. Results indicate that full-circuit executions are faster than circuit-splitting for simulations performed on a single node. However, circuit-splitting simulations show promising results in specific scenarios as the number of qubits is scaled.