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The Lifecycle of a Fault-Tolerant Quantum Computer

Rowan Brad Quni-Gudzinas

Published Dec 20, 2025• 0 citations
Publisher

Abstract

The operational lifetime of a fault-tolerant quantum computer is fundamentally a race between the inevitable, continuous degradation of its physical hardware and the escalating resource cost of the classical computation required for the error correction to compensate. This dynamic process defines a finite window of viability for any given quantum device. The initial quality of the processor’s qubits, defined by its system-environment coupling strength at manufacture ($\gamma_0$), does not determine whether this race will occur, but rather sets the starting line and influences the pace. Ultimately, every quantum computer is on a trajectory toward eventual obsolescence, either through physical failure when its error rate exceeds the fault-tolerance threshold, or through resource exhaustion as the cost of its own maintenance becomes computationally unsustainable.

DOI
10.5281/zenodo.18000789

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This thesis is concerned with certain theoretical problems that arise naturally in the context of fault-tolerant quantum computation. Fault-tolerance can be defined as the art of building reliable devices from unreliable components, and is of particular importance for quantum computers that aim to precisely control the dynamics of extremely sensitive quantum systems. A model of quantum computation is a specification of the basic building blocks by which a quantum computation is implemented. The best known model is the quantum circuit model, where computations are implemented by means of unitary quantum gates that are applied to two-level quantum systems known as qubits. In a physical implementation of a quantum circuit, the gates and qubits will inevitably be affected by noise. Fault-tolerant quantum circuits are designed to be resilient against the effects of this noise, provided that it is not too strong. Fault-tolerance in the quantum circuit model is well developed thanks to the theory of quantum error-correcting codes. These codes allow for the correction of small numbers of errors introduced by a variety of noise processes. In a fault-tolerant quantum circuit, qubits are replaced with encoded qubits, and quantum gates with encoded gates that are immediately followed by special quantum circuits for error correction. Provided the rate at which errors occur is below a constant threshold value, the accumulation of errors can be checked so that the correct output of the computation correctly determined. The threshold acts as both a measure of how good the design of a quantum circuit is, and also as a target for experimenters aiming to implement quantum circuits. Much current research in quantum computation is aimed at designing quantum circuits that increase the noise threshold, hopefully to the point where it becomes within the reach of experimenters. A fault-tolerant encoded quantum gate must limit the propagation of errors so that the code’s corrective capabilities are not overwhelmed. It is not so easy to design encoded gates that satisfy this property, and to date only a finite handful of such gates are known. In a faulttolerant quantum circuit, all quantum gates must be decomposed or compiled in terms of those that may be implemented fault-tolerantly. In the first part of this thesis, we present two results that may be applied to this problem of gate compilation. The first is a generic method based on the Solovay-Kitaev theorem that may be applied to all quantum gates, but is most effective for those that act on single qubits. We present the Solovay-Kitaev theorem in its simples known form as an algorithm, together with novel constructions that can be used to implement it. Following this we give a two specialized methods for two-qubit gate decomposition, based on the Cartan decomposition of the Lie group SU(4). The cluster-state model of computation is an alternative to the quantum circuit model, and makes use of quantum measurements and highly entangled cluster-states to implement a quantum computation. The fault-tolerant techniques developed for quantum circuits are not immediately applicable in this model, so in order for it to be a realistic candidate for performing computations we prove that such techniques are possible. In the second part of the thesis we prove that constant fault-tolerance thresholds may be achieved in the cluster-state model, and in particular in an adaption to an optical implementation. Following this we design a complete error correction scheme for optical cluster-state computation, and numerically determine the threshold of this model in the face of the dominant noise models likely to affect such an implementation.
In certain approaches to quantum computing the operations between qubits are nondeterministic and likely to fail. For example, a distributed quantum processor would achieve scalability by networking together many small components; operations between components should be assumed to be failure prone. In the ultimate limit of this architecture each component contains only one qubit. Here we derive thresholds for fault-tolerant quantum computation under this extreme paradigm. We find that computation is supported for remarkably high failure rates (exceeding 90%) providing that failures are heralded; meanwhile the rate of unknown errors should not exceed 2 in 10(4) operations.
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Quantum computation has the potential to solve certain mathematical and physical problems faster than a classical computer. However, one of the key challenges to realizing a quantum computing device is controlling systematic errors and maintaining the coherence of the quantum state. In addition, once a scalable quantum computer is built, we must be able to fault-tolerantly communicate a quantum algorithm to the physical device. In this dissertation, we take several significant steps towards the realization of a quantum computer. We develop a framework for use with any proposed technology to map a quantum algorithm into fault-tolerant machine instructions. Within this framework, we combat errors and decoherence by introducing quantum error correction and fault tolerance into a quantum circuit. We analyze specific fault-tolerant circuitry on two general architectures, nonlocal and nearest-neighbor, to determine failure thresholds of the physical circuit components. These failure thresholds allow physicists to evaluate technology proposals. Our goal is to provide design tools, failure thresholds, and fault-tolerant constructions to combat the faultiness of quantum computation.
We provide a basic introduction of the core ideas and theory surrounding fault-tolerant quantum computation. Quantum fault-tolerance essentially refers to avoiding the uncontrollable cascade of errors caused by the interaction of quantum-bits. The presented concepts underlay the theoretical framework of large-scale quantum computation and are the driving force for many recent experimental efforts to construct small to medium sized arrays of controllable quantum bits. We examine the basic principles of redundant quantum encoding, required to protect quantum bits from errors generated from both imprecise control and environmental interactions. The novelty of this work consists in the presentation of fault-tolerance principles from a classical distributed computing perspective, as this enables a more straightforward introduction without sacrificing generality. The practicality of fault-tolerant quantum computing is analysed after introducing a metric of scalability and discussing the factors influencing it.
Quantum computing is a field that shows tremendous possibilities and promise. It can provide an exponential speedup compared to classical computers in many computational problems, including simulations of general quantum mechanical systems, pattern finding and solving linear systems. Quantum computations can be performed by making use of qubits and performing operations, called gates, on them. A physical realisation of a qubit will be faulty, and to combat the errors that will inadvertently but unavoidably occur, the use of a quantum error correction code (QECC) is needed. A QECC is able to correct static errors; errors that occur on the states. However, it can not correct errors that occur on and during the operations. To make the computer resilient to these errors, the implementation of the QECC has to be performed fault-tolerantly. A fault-tolerant implementation of a quantum operation is designed in such a way that errors that happen during the operation, through faulty gates, do not propagate to errors on the states that are not correctable any more by the QECC. Hence, error propagation is a key concept in fault-tolerance. Every element of a general quantum circuit needs to be designed fault-tolerant. One of the elements that will be needed in any realistic quantum computer architecture is the possibility of exchanging the states of two qubits, so that an arbitrary pair of qubits can be brought physically close, allowing the implementation of multi-qubit gates. Exchanging the states of two qubits can be performed by a fault-tolerant SWAP gate, that makes use of one ancilla qubit. In this thesis, a fault-tolerant SWAP operation is implemented on the IBM 5-qubit ‘Tenerife’ device. It is characterized as a quantum channel by performing quantum process tomography (QPT). The CPTP constraints of quantum channels in the framework of QPT are discussed and a method of obtaining a CPTP estimate of an initial QPT reconstruction is given. The error process of the fault-tolerant SWAP is analysed and subsequently compared to a normal implementation of the SWAP gate, on which tomography is performed as well. The main measure that is used in the comparison is the ratio r of multi-qubit errors (or correlated) to single-qubit (or uncorrelated) errors in the two implementations. SPAM errors are an important source of estimated infidelity. To filter these SPAM errors and obtain a better estimate of only the circuits, SPAM errors are approximated to be only measurement errors. The errors are characterized by performing tomography on an arbitrary short identity channel, and subsequently using this as an estimate of the measurement error map. This gives a method to estimate a representation of the circuit itself. We can report on an error ratio r of 0.170±0.0029 for the fault-tolerant SWAP operation and an error ratio r of 1.256 ± 0.0129 for the non-fault-tolerant SWAP operation. However, the total error in the fault-tolerant SWAP is much higher, resulting in a process fidelity Fp = 0.608 for the fault-tolerant implementation and Fp = 0.742 for the normal implementation. This is due to the larger number of gates in the fault-tolerant circuit. This research shows that a SWAP operation can be implemented fault-tolerantly, but that the error rates of the devices need to be reduced before their use becomes viable.