Quantum computing holds the potential to efficiently solve certain problems believed to be intractable for classical computers. Realizing this potential, however, requires substantial physical resources, including large qubit counts, sufficient connectivity, and long coherence times. As current quantum devices are still far from this regime, the efficient compilation of quantum algorithms into hardware-compatible instructions remains a central challenge in quantum computing, especially for near-term applications. A representative example of such applications is combinatorial optimization, where exponentially large search spaces motivate quantum algorithms that leverage interference to approximate solutions more efficiently than classical heuristics, even at modest system sizes. Two prominent paradigms in this context are quantum annealing and the Quantum Approximate Optimization Algorithm (QAOA): Quantum annealing realizes optimization via continuous-time quantum dynamics implemented on analog hardware, while QAOA is a variational, gate-based approach that builds parameterized quantum circuits from problem-specific Hamiltonians. Both paradigms require compilation strategies tailored to the constraints of their respective hardware architectures. Most existing compilation strategies are problem-agnostic and therefore broadly applicable, yet often suboptimal for specific tasks. This thesis uses the graph coloring problem as a case study to investigate a problem-driven approach to quantum compilation, where structural features of the problem class are exploited to design tailored compilation schemes that offer improved efficiency and scalability for the targeted application. To address hardware connectivity constraints, the presented approaches adopt the parity framework, which encodes long-range interactions into single-qubit terms. This thesis develops two novel problem-driven compilation methods for the graph coloring problem, the Bandwidth-Optimized LHZ layout and the 2D-Twine circuit. The former leverages bandwidth minimization to optimize parity encodings for analog quantum annealers, while the latter constructs QAOA unitaries for gate-based optimization using parallelized Parity Twine circuits. Both approaches are benchmarked against general-purpose methods and demonstrate substantial improvements in qubit usage or circuit complexity. These results illustrate the advantages of incorporating problem structure into the compilation process and provide a proof-of-concept for the effectiveness of problem-driven compilation strategies.
Quantum computing holds the potential to efficiently solve certain problems believed to be intractable for classical computers. Realizing this potential, however, requires substantial physical resources, including large qubit counts, sufficient connectivity, and long coherence times. As current quantum devices are still far from this regime, the efficient compilation of quantum algorithms into hardware-compatible instructions remains a central challenge in quantum computing, especially for near-term applications. A representative example of such applications is combinatorial optimization, where exponentially large search spaces motivate quantum algorithms that leverage interference to approximate solutions more efficiently than classical heuristics, even at modest system sizes. Two prominent paradigms in this context are quantum annealing and the Quantum Approximate Optimization Algorithm (QAOA): Quantum annealing realizes optimization via continuous-time quantum dynamics implemented on analog hardware, while QAOA is a variational, gate-based approach that builds parameterized quantum circuits from problem-specific Hamiltonians. Both paradigms require compilation strategies tailored to the constraints of their respective hardware architectures. Most existing compilation strategies are problem-agnostic and therefore broadly applicable, yet often suboptimal for specific tasks. This thesis uses the graph coloring problem as a case study to investigate a problem-driven approach to quantum compilation, where structural features of the problem class are exploited to design tailored compilation schemes that offer improved efficiency and scalability for the targeted application. To address hardware connectivity constraints, the presented approaches adopt the parity framework, which encodes long-range interactions into single-qubit terms. This thesis develops two novel problem-driven compilation methods for the graph coloring problem, the Bandwidth-Optimized LHZ layout and the 2D-Twine circuit. The former leverages bandwidth minimization to optimize parity encodings for analog quantum annealers, while the latter constructs QAOA unitaries for gate-based optimization using parallelized Parity Twine circuits. Both approaches are benchmarked against general-purpose methods and demonstrate substantial improvements in qubit usage or circuit complexity. These results illustrate the advantages of incorporating problem structure into the compilation process and provide a proof-of-concept for the effectiveness of problem-driven compilation strategies.
Quantum computing capabilities have developed rapidly in the last years, both in terms of experimental control of quantum systems and theoretical knowledge of quantum algorithms. During this time, the field has progressed from few-qubit prototypes to small computers that can do non-trivial calculations. In a few cases, these calculations approach the current limits of what classical computers can achieve. At this point in time, it is critical to get the maximal performance out of the available quantum hardware, which requires practical applications, smart algorithms, error mitigation and powerful decoding strategies. One near-term application of these quantum devices is quantum optimization, which utilizes quantum computers to solve combinatorial optimization problems. The way these problems are encoded on the quantum device is crucial and often requires both hardware-independent as well as hardware-specific ideas. A core part of this process is compilation, which translates the high-level quantum algorithm to instructions that can be executed on the physical quantum computer. In this thesis we focus on a specific kind of compilation, which originates from the Lechner-Hauke-Zoller model. We present the parity architecture, which is a hardware-independent way to compile arbitrary combinatorial optimization problems to quantum systems. With the parity architecture, analog and digital quantum algorithms can be executed using only local interactions, at the cost of a qubit overhead. First, we introduce a mathematical framework for the parity compiler using linear algebra and give some practical examples. This framework also allows the encoding of higher-order interactions directly, without the need to convert them to quadratic terms. We then benchmark the resource requirements of the parity architecture for digital algorithms, comparing against standard methods that use qubit routing. After that, we show how to compile for digital quantum devices with arbitrary connectivity. Here, we relax the condition that the interactions in the parity architecture are all completely local, resulting in a more flexible compilation approach. Finally, we show that parity compilation can be done constructively for any optimization problem at the cost of a qubit overhead. This qubit overhead can then be minimized by performing a search through different configurations.
Quantum computers hold the promise of solving certain computational problems significantly faster than classical computers. Unlocking the full potential of quantum hardware depends on our ability to efficiently translate high-level quantum algorithms into executable sequences of quantum operations tailored to the specific constraints of a given device, a task known as quantum compilation. Among the most promising applications is the simulation of quantum systems, such as in quantum chemistry, where scalable, error resilient, and experimentally feasible Hamiltonian simulation techniques are essential. In the first part of this thesis, we present recent advances in the field of quantum compilation, emphasizing on efficient gate decomposition and circuit optimization. In particular, we analyze compilation techniques for Clifford circuits and general single-qubit rotations. Clifford operations play a central role in quantum error correction, the characterization of quantum devices and quantum cryptography. We explore asymptotically optimal decomposition methods, including constructions using either two-qubit gates or global entangling operations, the latter being especially well-suited for platforms like trapped ions. For single-qubit unitaries, we discuss approximation schemes that achieve the theoretically optimal scaling of gate count with respect to the desired precision. Beyond gate synthesis, we examine various hardware-aware optimization strategies aimed at reducing circuit depth and gate overhead. These include techniques for qubit routing in systems with limited connectivity, as well as methods for removing redundant operations. The second and primary, scientific contribution of this thesis focuses on implementation of effective many-body interactions on quantum hardware by combining the system’s native dynamics with control operations, which we call Hamiltonian engineering. Motivated by the central role of Hamiltonian simulation in quantum science, we introduce a general and efficient framework for synthesizing arbitrary target Hamiltonians under mild locality constraints. We propose a novel linear programming (LP) approach that computes pulse sequences consisting of single-qubit π or π/2 rotations applied at certain times during free evolution under the system’s native Hamiltonian. Our LP-based framework offers multiple advantages. First, its classical runtime depends only on the number and locality of the interactions in the system Hamiltonian, not directly on the overall system size. Second, we extend the method to include robustness against common error sources such as finite pulse time effects and systematic control errors, leveraging tools from average Hamiltonian theory and robust composite pulses. Our approach enables the efficient realization of high-fidelity Hamiltonian dynamics with minimal experimental overhead. The scalability of the approach are demonstrated through simulations, including the engineering of a random two-body Hamiltonian on a 225 qubit lattice in under a minute of classical preprocessing. In conclusion, this thesis contributes both theoretical insights and practical tools that bridge the gap between algorithm design and experimental implementation in quantum computing. The techniques developed here are directly applicable to a variety of platforms, including trapped ions, neutral atoms, and superconducting circuits. By advancing the frontiers of Hamiltonian engineering, this work enables more efficient, robust, and scalable quantum simulations on nearterm devices. Finally, it brings us closer to realizing quantum technologies, which are possibly capable of solving meaningful problems.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
Graph coloring is a well-known combinatorial optimization problem with broad applications in network security, scheduling, and register allocation. Being an NP-hard problem, exact solutions for large instances are computationally infeasible, calling for other solution strategies. In this study, parameterized and approximation methods to tackle the graph coloring problem are investigated. While approximation algorithms yield near-optimal solutions with theoretical guarantees of performance that are well-suited for large-scale applications, parameterized algorithms utilize graph-specific structural properties to manage constrained instances efficiently. We examine the trade-offs in these approaches, highlighting their strengths and weaknesses. In addition, we introduce a hybrid approach that combines both parameterized and approximation methods to best optimize computational resources and balance accuracy versus feasibility. Furthermore, we discuss the newly realized potential of quantum computing—specifically quantum annealing and the Quantum Approximate Optimization Algorithm (QAOA)—to speed up graph coloring by leveraging quantum parallelism and state superposition. Such quantum-based techniques represent a promising line of attack for breaking up large and hard instances that overwhelm classical approaches. Future research will aim to tighten approximation guarantees, create quantum-augmented hybrid models, and test theoretical results against real-world datasets.
Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.
Graph coloring is a well-known NP-complete problem with applications in scheduling, register allocation, frequency assignment, and network optimization. Quantum computing offers the potential for polynomial or even super-polynomial speedups in certain problem instances, yet practical quantum graph coloring methods must carefully balance qubit resources, circuit depth, and constraint enforcement. We proposed a solver agnostic quantum framework for K-coloring. Along with a novel encoding and efficient constraint implementation for its exact coloring exploiting Grover search and almost optimal coloring by the Quantum Approximate Optimization Algorithm \emph{(QAOA)}, and \emph{Quantum Annealing}. Unlike using O(NK) qubits as in \emph{SOTA}, we reduced the qubit requirements to O(Nlog2K), along with optimized comparator circuits enforcing adjacency constraints. Further symmetry-based graph reduction is incorporated as an optional preprocessing step to further reduce the instance size before quantum execution.